Structure comprising a thin layer of material made up of conductive zones and insulating zones and a method of manufacturing such a structure

• US 6,362,077 B1
• Filed: 10/06/1999
• Issued: 03/26/2002
• Est. Priority Date: 10/16/1998
• Status: Expired due to Term

• Current Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Original Assignee: Commissariat A L'Atomique
• Inventors: Jalaguier, Eric, Aspar, Bernard, Bruel, Michel
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): RICHARDS, NORMAN DREW
• Application Number:
  US09/413,483
• Time in Patent Office: 902 Days
• Field of Search: 438/455, 438/458, 438/459, 438/67, 438/518, 438/520
• US Class Current: 438/458
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A structure comprising a thin layer (2) that can be integral with a support (3), the thin layer being a layer of a semiconductor material made insulating by ion implantation except for at least one zone that permits a vertical electrical connection through the entire thickness of the thin layer (2). A method of manufacturing such a structure is also disclosed.

Claims

1. Method of manufacturing a thin layer which operates as at least one vertical electrical connection through its entire thickness, the thin layer comprising a conductive or semiconductive material whose electrical properties are disruptable by ion implantation using a predetermined implantation species, the method comprising:

masking one face of a substrate comprising said material by masking means that define at least one masked area, the size of said masked area not exceeding a predetermined limiting dimension beyond which crack propagation is modified such that proper cleavage is inhibited;

performing ion implantation of the substrate through said masked face by means of said predetermined implantation species to thereby create, within a non-masked volume of the substrate and at a depth close to a mean depth of penetration of said predetermined implantation species, a layer of micro-cavities demarcating said thin layer;

removing the masking means; and

cleaving the substrate at the depth of the layer of micro-cavities in order to obtain said thin layer.

2. Method according to claim 1, characterized in that the implanted face of the substrate is made integral with a support before the cleavage step.

3. Method according to claim 1, characterized in that the thin layer is made integral with a support after the cleavage step.

4. Method according to claim 1, characterized in that the masking means comprise deposits of a material capable of preventing penetration of the ions into the substrate during the ion implantation, these deposits being deposited on said face of the substrate.

5. Method according to claim 1, characterized in that the masking means comprise micro-elements deposited on said face of the substrate.

6. Method according to claim 5, characterized in that said micro-elements are chosen from among micro-beads and particles.

7. Method according to claim 1 characterized in that the masking is carried out in such a way that the thin layer overall preserves the electrical properties of the substrate.

8. Method according to claim 1 characterized in that the masking is carried out in such a way that the thin layer overall behaves like an insulating layer except for at least one part formed from one zone or from several neighboring zones preserving the electrical properties of the substrate.

9. Method according to claim 8, characterized in that the part formed from this zone or from several neighboring zones preserving the electrical properties of the substrate constitutes a conductive path or a conductive track.

10. Method according to claim 2, characterized in that the step of integrating the substrate with the support is carried out by a method chosen between bonding by molecular adhesion and bonding by means of a brazing material.

11. Method according to claim 10, characterized in that said brazing material is based on indium.

12. Method according to claim 2, characterized in that it includes, before the integration step, a step of preparing a conductive interface between said face of the substrate and said support.

13. Method according to claim 12, characterized in that the step of preparing a conductive interface comprises the deposition of a metal layer onto said face of the substrate and/or onto the support.

14. Method according to claim 13, characterized in that the said metal layer is a layer of palladium.

15. Method according to claim 13, characterized in that said interface metal layer is associated with the deposition of conductive metal bonding materials.

16. Method according to claim 15, characterized in that the conductive bonding materials are successive deposits of titanium, nickel and gold.

17. Method according to of claim 13, characterized in that a heat treatment is carried out in a way that causes diffusion of the deposited metal layer.

18. Application of the method according to claim 1 to the manufacture of a structure comprising a thin layer of SiC, GaAs or InP on a support, the ion implantation being carried out using hydrogen and/or helium ions.

19. Application according to claim 18, characterized in that the support is made of silicon.

20. Method according to claim 3, characterized in that the masking means comprise deposits of a material capable of preventing penetration of the ions into the substrate during the ion implantation, these deposits being deposited on said face of the substrate.

21. Method according to claim 6, characterized in that the masking is carried out in such a way that the thin layer overall preserves the electrical properties of the substrate.

22. Method according to claim 6, characterized in that the masking is carried out in such a ways that the thin layer overall behaves like an insulating layer except for at least one part formed from one zone or from several neighboring zones preserving the electrical properties of the substrate.

23. Method according to claim 14, characterized in that said interface metal layer is associated with the deposition of conductive metal bonding materials.

24. Method according to claim 16, characterized in that a heat treatment is carried out in a way that causes diffusion of the deposited metal layer.

25. Application of the method according to claim 17 to the manufacture of a structure comprising a thin layer of SiC, GaAs or InP on a support, the ion implantation being carried out using hydrogen and/or helium ions.