Methodology for control of short channel effects in MOS transistors

• US 6,362,082 B1
• Filed: 06/28/1999
• Issued: 03/26/2002
• Est. Priority Date: 06/28/1999
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Doyle, Brian S., Roberds, Brian
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): LE, DUNG ANH
• Application Number:
  US09/342,030
• Time in Patent Office: 1,002 Days
• Field of Search: 438/523, 438/243, 438/270, 438/267, 438/291, 438/301, 438/364-367, 438/370, 438/371
• US Class Current: 438/523
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26533 of electrically inactive species in silicon to make buried insulating layers
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054

Abstract

A method of improving short channel effects in a transistor. First, a substance is implanted in a substrate. The substrate is then annealed such that the implanted substance forms at least one void in the substrate. Then, a transistor having a source, a drain, and a channel region is formed on the substrate, wherein the at least one void is in the channel region of the transistor.

Claims

1. A method to improve a short channel effect in a transistor comprising:

implanting a substance in a substrate;

annealing said substrate such that said implanted substance forms a void in said substrate; and

,

forming a transistor on said substrate, in which a channel region of said transistor includes said void to inhibit lines of force from a drain of said transistor from terminating at a source of said transistor.

2. The method of claim 1 wherein implanting said substance further comprises implanting said substance selected from the group consisting of the noble gases, oxygen, and any combination thereof.

3. The method of claim 1 wherein implanting said substance further comprises implanting at an energy level of approximately 30 keV.

4. The method of claim 3 wherein implanting said substance further comprises implanting a gaseous substance at a dosage of approximately 10¹⁶ to 10¹⁷ atoms/cm².

5. The method of claim 1 wherein said step of annealing said substrate further comprises annealing at a temperature of at least 400°

C.

6. The method of claim 5 wherein annealing said substrate further comprises annealing for at least 30 seconds.

7. The method of claim 1 wherein annealing said substrate further comprises annealing at a temperature of approximately 1100°

C.

8. The method of claim 7 wherein annealing said substrate further comprises annealing for at least 30 seconds.

9. The method of claim 1 wherein said void is located approximately in a center of said channel region.

10. The method of claim 9 wherein said void provides termination for said lines of force to reduce leakage current between said source and said drain.

11. The method of claim 1 in which a plurality of voids are formed in said channel region.

12. The method of claim 11 wherein said voids are located in said channel region adjacent said source and said drain.

13. The method of claim 12 wherein said voids provide termination for said lines of force to reduce leakage current between said source and said drain.

14. A method to improve a short channel effect in a transistor comprising:

implanting a gaseous substance in a substrate;

annealing said substrate such that said implanted gaseous substance forms a void in said substrate;

forming a transistor on said substrate, in which a channel region of said transistor includes said void to inhibit lines of force from a drain of said transistor from terminating at a source of said transistor; and

,

having said void provide a barrier for said lines of force between said source and said drain to reduce leakage current.

15. The method of claim 14 wherein implanting said gaseous substance further comprises implanting said gaseous substance selected from the group consisting of the noble gases, oxygen, and any combination thereof.

16. The method of claim 14 wherein implanting said gaseous substance further comprises implanting at an energy level of approximately 30 KeV.

17. The method of claim 16 wherein implanting said gaseous substance further comprises implanting a gaseous substance at a dosage of approximately 10¹⁶ to 10¹⁷ atoms/cm².

18. The method of claim 14 wherein annealing said substrate further comprises annealing at a temperature of at least 400°

C.