Nickel silicide stripping after nickel silicide formation
First Claim
Patent Images
1. A method of manufacturing a semiconductor device, comprising the steps of:
- providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions and a gate oxide between the gate electrode and the substrate;
forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls;
forming nickel silicide layers disposed on the source/drain regions and the gate electrode;
etching with a first etchant to remove unreacted nickel from the semiconductor device; and
etching with a second etchant to remove nickel silicide formed over the first and second sidewall spacers, wherein the first etchant is different than the second etchant and has a high selectivity to nickel and the second etchant has a high selectivity to nickel silicide.
1 Assignment
0 Petitions
Accused Products
Abstract
A method of manufacturing a MOSFET semiconductor device comprises providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions; providing a gate oxide between the gate electrode and the substrate; forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls; forming nickel silicide layers disposed on the source/drain regions and the gate electrode, and two etching steps. The nickel silicide layers are formed during a rapid thermal anneal at temperatures from about 380 to 600° C. The first etch is performed with a sulfuric peroxide mix to remove unreacted nickel, and the second etch is performed with an ammonia peroxide mix to remove nickel silicide formed over the first and second sidewall spacers.
18 Citations
16 Claims
-
1. A method of manufacturing a semiconductor device, comprising the steps of:
-
providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions and a gate oxide between the gate electrode and the substrate;
forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls;
forming nickel silicide layers disposed on the source/drain regions and the gate electrode;
etching with a first etchant to remove unreacted nickel from the semiconductor device; and
etching with a second etchant to remove nickel silicide formed over the first and second sidewall spacers, wherein the first etchant is different than the second etchant and has a high selectivity to nickel and the second etchant has a high selectivity to nickel silicide. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A method of manufacturing a MOSFET semiconductor device, comprising the steps of:
-
providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions and a gate oxide between the gate electrode and the substrate;
forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls;
forming nickel silicide layers disposed on the source/drain regions and the gate electrode, the nickel silicide layers formed during a rapid thermal anneal at temperatures from about 380 to 600°
C.;
etching with a sulfuric peroxide mix to remove unreacted nickel from the semiconductor device; and
etching with an ammonia peroxide mix to remove nickel silicide formed over the first and second sidewall spacers.
-
-
9. A method of manufacturing a semiconductor device having two conductive portions separated by a spacer, comprising the steps of:
-
forming a metal silicide on the semiconductor device;
removing unreacted metal from the semiconductor device; and
removing a thickness of about 10 to 30 angstroms of the metal silicide from the conductive portions and substantially all of the metal silicide from the spacer. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
-
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
-
Current AssigneeAdvanced Micro Devices, Inc.
-
Original AssigneeAdvanced Micro Devices, Inc.
-
InventorsWoo, Christy Mei-Chu, Kluth, George Jonathan, Bertrand, Jacques
-
Primary Examiner(s)Bowers, Charles
-
Assistant Examiner(s)PHAM, THANHHA S
-
Application NumberUS09/679,876Time in Patent Office537 DaysField of Search438/299, 438/229, 438/230, 438/233, 438/300, 438/303, 438/581, 438/583, 438/630, 438/649, 438/651, 438/655, 438/663, 438/664, 438/682, 438/683, 438/721, 438/745, 438/755, 438/754US Class Current438/649CPC Class CodesH01L 21/28518 the conductive layers compr...H01L 29/665 using self aligned silicida...
