Field effect transistor with organic semiconductor layer

• US 6,362,509 B1
• Filed: 10/06/2000
• Issued: 03/26/2002
• Est. Priority Date: 10/11/1999
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Royal Philips Electronics NV (Koninklijke Philips N.V.)
• Inventors: Hart, Cornelis Maria
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): WILSON, CHRISTIAN D
• Application Number:
  US09/684,301
• Time in Patent Office: 536 Days
• Field of Search: 257/40, 257/202, 257/208, 257/307, 257/369, 438/99
• US Class Current: 257/369
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H10K 10/462 Insulated gate field-effect transistors [IGFETs]
• CPC Class Codes: H10K 10/82 Electrodes
• CPC Class Codes: H10K 19/10 comprising field-effect transistors
• CPC Class Codes: H10K 71/60 Forming conductive regions or layers, e.g. electrodes
• CPC Class Codes: H10K 85/10 Organic polymers or oligomers
• CPC Class Codes: H10K 85/111 comprising aromatic, heteroaromatic, or aryl chains, e.g. polyaniline, polyphenylene or polyphenylene vinylene
• CPC Class Codes: H10K 85/113 Heteroaromatic compounds comprising sulfur or selene, e.g. polythiophene
• CPC Class Codes: H10K 85/114 Poly-phenylenevinylene; Derivatives thereof

Abstract

The integrated circuit (1) suppresses leakage currents, which usually take place between neighboring transistors (10, 20) through the unpatterned semiconductor layer (5). In its first layer (3), the circuit (10) comprises electrically conductive tracks (4) which are in contact with the semiconductor layer (5), some of which tracks (4) are in use as source and drain electrodes (14, 15, 24, 25) and are preferably fork-shaped and interdigitated. The suppression of leakage currents is achieved by putting neighboring electrodes (14, 24) in different transistors (10, 20) at the same voltage and by excluding the presence of any other electrically conductive tracks between those neighboring electrodes (14, 24). Interconnect lines (39) carrying input or output signals are positioned in a second layer (7) as much as possible, which second layer (7) comprises electrically conductive tracks (8) and is not in contact with the semiconductor layer (5). The integrated circuit (1) of the invention is very well fitted to contain arrays of NAND structures.

Claims

1. An integrated circuit (1) comprising a substrate (2) with an electrically insulating surface, on which surface are present:

an insulating layer (6);

a semiconducting layer (5) which is at least substantially unpatterned;

a first patterned layer (3) comprising a pattern of electrical conductors (4); and

a second patterned layer (7) which comprises a pattern of electrical conductors (8) and which is separated from the first patterned layer (3) and from the semiconducting layer (5) by the insulating layer (6),

wherein the first patterned layer (3) is in contact with the semiconducting layer (5) and comprises a first (10) and a second transistor (20), said first and second transistors (10, 20) each having a first (14, 24) and a second electrode (15, 25), of which electrodes (14, 24;

15, 25) at least the first electrodes (14, 24) comprise a number of electrically conducting tracks (61, 62;

63, 64) which are at least substantially parallel, characterized in that

the first electrode (14) of the first transistor (10) and the first electrode (24) of the second transistor (20) both perform the same function of source and drain electrode;

the circuit (1) comprises means for giving the first electrode (14) of the first transistor (10) and the first electrode (24) of the second transistor (20) in the first patterned layer (3) the same potential in operational condition; and

the first patterned layer (3) between the first (10) and the second transistor (20) is free from any electrical conductor which has a potential other than that of the first electrode (14) of the first transistor (10) in the operational condition.

2. An integrated circuit (1) as claimed in claim 1, characterized in that said means comprise an electrical conductor (291) in the first patterned layer (3), which conductor (291) interconnects the first electrodes (14, 24) of the first (10) and the second transistor (20).

3. An integrated circuit (201) as claimed in claim 2, characterized in that

the first electrode (214) and the second electrode (215) of the first transistor (210) are interdigitated and together form a pair (213), which pair (213) has a number of at least substantially parallel electrically conducting tracks (261, 262, 263, 264, 271, 272, 273); and

two outermost tracks (261, 264) of the interdigitated pair (213) belong to the first electrode (214).

4. An integrated circuit as claimed in claim 3, characterized in that the first electrode (214) has at least three tracks (261, 262, 263, 264), of which two outermost tracks (261, 264) are the longest.

5. An integrated circuit as claimed in claim 2, characterized in that

the conductor interconnecting the first electrodes (14, 24) is a first supply line (91);

the first (10) and the second transistor (20) form part of a first NAND function block (51), which NAND function block (51) in addition comprises a third transistor (30);

the NAND function block (51) comprises an interdigitated pair (33) of a source and a drain electrode (34, 35) of the third transistor (30) in the first patterned layer (3), of which pair (33) a first electrode (34) is connected to a second supply line (92), such that the NAND function block (51) lies between the first (91) and the second supply line (92) in as far as this block (51) is present in the first patterned layer (3); and

the second supply line (92) interconnects the first electrode (34) of the third transistor (30) and a first electrode of a second NAND function block.

6. An integrated circuit as claimed in claim 1, characterized in that the electrical conductor (19) which transfers signals chosen from the group of input signals and output signals to the first transistor (10) is present in the second patterned layer (7).

7. An integrated circuit (101) as claimed in claim 1, characterized in that an auxiliary conductor (183) in contact with one of the supply lines (91, 92) lies between a first (181) and a second electrical conductor (182) in the first patterned layer, the latter two conductors (181, 182) being situated outside a transistor.

8. An integrated circuit as claimed in claim 1, characterized in that at least one patterned layer (3, 7) is constructed so as to have a relief structure.

9. An integrated circuit as claimed in claim 1, characterized in that the semiconducting layer (5) mainly comprises organic material.

10. An integrated circuit as claimed in claim 1, characterized in that at least one patterned layer (3, 7) comprises mainly organic polymeric material.