Circuit structure including a passive element formed within a grid array substrate and method for making the same

• US 6,362,525 B1
• Filed: 11/09/1999
• Issued: 03/26/2002
• Est. Priority Date: 11/09/1999
• Status: Expired due to Term

• Current Assignee: Deca Technologies Incorporated (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Rahim, Irfan M.
• Primary Examiner(s): Williams, Alexander O.
• Application Number:
  US09/436,914
• Time in Patent Office: 868 Days
• Field of Search: 257/737, 257/738, 257/728, 257/723, 257/724, 257/700, 257/701, 257/777-782, 257/686, 257/685, 257/787, 257/788, 257/690, 257/691, 257/774, 257/528, 257/531, 361/767, 361/760, 361/764, 361/765, 438/381, 438/238
• US Class Current: 257/738
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/81385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19103 : interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 1/025 : Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance H05K1/024 and H05K1/0243 take precedence; for semiconductor devices H01L23/66
• CPC Class Codes: H05K 1/165 : incorporating printed inductors
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components

Abstract

A circuit structure combines an integrated circuit with a passive circuit element formed within a grid-array substrate. Formation of the circuit structure includes forming a passive circuit element within one or more conductive layers of a grid-array substrate such as may be used for packaging of integrated circuits. A pair of terminals of the passive circuit element is coupled to a pair of passive element contact pads within a processed surface of the integrated circuit, thereby connecting the integrated circuit to the grid-array substrate. The same grid-array substrate may be used for formation of the passive circuit element and for packaging of the integrated circuit. In some embodiments the lateral extent of the integrated circuit overlaps the lateral extent of the passive circuit element. Alternatively, the passive circuit element may be laterally displaced from the integrated circuit. A low-loss substrate may be mounted onto the grid-array substrate, and laterally displaced from the integrated circuit such that the lateral extent of the low-loss substrate overlaps that of the passive circuit element.

Claims

1. A circuit structure, comprising:

a grid-array substrate comprising a first conductive layer;

a passive circuit element formed at least in part within the first conductive layer, wherein the passive circuit element comprises a pair of terminals; and

a semiconductor-based integrated circuit having a processed surface facing a surface of the grid-array substrate, wherein a pair of passive element contact pads within the processed surface is coupled to the pair of terminals, respectively, and wherein the passive circuit element is laterally displaced from the semiconductor-based integrated circuit.

2. The circuit structure as recited in claim 1, wherein the first conductive layer comprises copper.

3. The circuit structure as recited in claim 1, wherein the first conductive layer has a thickness greater than approximately five microns.

4. The circuit structure as recited in claim 1, wherein the first conductive layer forms a portion of the surface of the grid-array substrate.

5. The circuit structure as recited in claim 1, wherein the grid-array substrate further comprises an insulating layer between the first conductive layer and the surface of the grid-array substrate.

6. The circuit structure as recited in claim 1, wherein a connection between one of the pair of passive element contact pads and one of the pair of terminals comprises a solder ball.

7. The circuit structure as recited in claim 1, wherein the passive circuit element comprises an inductor.

8. The circuit structure as recited in claim 1, wherein the passive circuit element comprises a transmission line.

9. The circuit structure as recited in claim 1, wherein the grid-array substrate further comprises a second conductive layer and an insulating layer interposed between the first and second conductive layers, and wherein the passive circuit element is formed at least in part within a combination of the first and second conductive layers and the insulating layer.

10. The circuit structure as recited in claim 9, wherein the passive circuit element comprises a capacitor.

11. The circuit structure as recited in claim 1, further comprising a low-loss substrate coupled to the surface of the grid-array substrate, wherein the low-loss substrate is laterally displaced from the semiconductor-based integrated circuit, and wherein a lateral extent of the low-loss substrate overlaps a lateral extent of the passive circuit element.

12. The circuit structure as recited in claim 11, wherein the low-loss substrate comprises alumina.

13. The circuit structure as recited in claim 1, wherein said semiconductor-based integrated circuit comprises a silicon-based integrated circuit.

14. A method for forming a circuit structure, comprising:

forming at least a portion of a passive circuit element within a conductive layer of a grid-array substrate;

coupling a pair of terminals within the passive circuit element to a pair of passive element contact pads within a processed surface of a semiconductor-based integrated circuit, such that the processed surface faces a surface of the grid-array substrate; and

coupling a low-loss substrate to the surface of the grid-array substrate.

15. The method as recited in claim 14, wherein said forming at least a portion comprises patterning the conductive layer.

16. The method as recited in claim 15, wherein said forming at least aportion further comprises:

forming a dielectric layer over the patterned conductive layer; and

forming a pair of conductive vias between the pair of terminals, respectively, and the surface of the grid-array substrate.

17. The method as recited in claim 14, wherein said coupling a pair of terminals comprises positioning a pair of solder balls between the pair of terminals and the pair of passive element contact pads, respectively.

19. The method as recited in claim 14, wherein said coupling the low-loss substrate comprises laterally displacing the low-loss substrate from the semiconductor-based integrated circuit.

18. A method for forming a circuit structure, comprising coupling a pair of passive element contact pads within a semiconductor-based integrated circuit to a pair of terminals within a passive circuit element formed within a grid-array substrate, wherein a surface of the integrated circuit containing the passive element contact pads is oriented to face a surface of the grid-array substrate, and wherein said coupling a pair of passive element contact pads comprises laterally displacing the semiconductor-based integrated circuit from the passive circuit element to reduce interaction between the integrated circuit and an electromagnetic field generated by the passive circuit element.

20. The method of as recited 14, wherein said coupling the low-loss substrate comprises overlapping a lateral extent of the low-loss substrate over a lateral extent of the passive circuit element.