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Integrated defect monitor structures for conductive features on a semiconductor topography and method of use

  • US 6,362,634 B1
  • Filed: 01/14/2000
  • Issued: 03/26/2002
  • Est. Priority Date: 01/14/2000
  • Status: Expired due to Fees
First Claim
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1. A test structure comprising:

  • a first conductive line formed at a first conductive feature layer of an integrated circuit topography;

    a second conductive line formed at a second conductive feature layer of the integrated circuit topography; and

    a daisy chain conductive feature, comprising first conductive line segments formed at the first conductive feature layer and second conductive line segments formed at the second conductive feature layer, wherein the first conductive line segments and the second conductive line segments are interconnected by vias formed vertically through a dielectric layer separating the first conductive feature layer from the second conductive feature layer;

    wherein the first conductive line, the second conductive line and the daisy chain conductive feature are electrically isolated from each other in the absence of a defect.

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