Integrated defect monitor structures for conductive features on a semiconductor topography and method of use
First Claim
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1. A test structure comprising:
- a first conductive line formed at a first conductive feature layer of an integrated circuit topography;
a second conductive line formed at a second conductive feature layer of the integrated circuit topography; and
a daisy chain conductive feature, comprising first conductive line segments formed at the first conductive feature layer and second conductive line segments formed at the second conductive feature layer, wherein the first conductive line segments and the second conductive line segments are interconnected by vias formed vertically through a dielectric layer separating the first conductive feature layer from the second conductive feature layer;
wherein the first conductive line, the second conductive line and the daisy chain conductive feature are electrically isolated from each other in the absence of a defect.
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Abstract
A test structure which includes a first conductive feature layer and a second conductive feature layer is described. The first conductive feature layer includes a first conductive line. The second conductive feature layer includes a second conductive line. A daisy chain conductive feature is also included in the test structure. The daisy chain conductive feature includes portions on the first and second conductive feature layers which are interconnected to each other by vias.
46 Citations
22 Claims
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1. A test structure comprising:
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a first conductive line formed at a first conductive feature layer of an integrated circuit topography;
a second conductive line formed at a second conductive feature layer of the integrated circuit topography; and
a daisy chain conductive feature, comprising first conductive line segments formed at the first conductive feature layer and second conductive line segments formed at the second conductive feature layer, wherein the first conductive line segments and the second conductive line segments are interconnected by vias formed vertically through a dielectric layer separating the first conductive feature layer from the second conductive feature layer;
wherein the first conductive line, the second conductive line and the daisy chain conductive feature are electrically isolated from each other in the absence of a defect. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for detecting defects produced during the formation of an integrated circuit, comprising:
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forming a first conductive line on a first conductive feature layer;
forming a second conductive line on a second conductive feature layer, where the first and second feature layers are separated by a dielectric;
forming a daisy chain conductive feature including first line segments within the first conductive feature layer and second line segments within the second conductive feature layer, where the first and second line segments are interconnected by vias extending through the dielectric; and
determining an electrical resistance between first and second test pads among a plurality of test pads coupled to the first conductive line, the second conductive line and the daisy chain feature. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A test structure for detecting the presence of defects in conductive features formed on an integrated circuit topography comprising a planar serpentine conductive line and a daisy chain conductive feature, wherein the daisy chain conductive feature extends partially coplanar with and laterally from the serpentine conductive line and partially on a plane above or below a plane of the first serpentine line.
Specification