Low supply voltage relaxation oscillator having current mirror transistors supply for capacitors

• US 6,362,697 B1
• Filed: 04/28/2000
• Issued: 03/26/2002
• Est. Priority Date: 04/30/1999
• Status: Expired due to Term

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Pulvirenti, Francesco
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US09/561,425
• Time in Patent Office: 697 Days
• Field of Search: 331/111, 331/113.R, 331/143-145
• US Class Current: 331/111
• CPC Class Codes: H03K 3/03 Astable circuits
• CPC Class Codes: H03K 3/354 Astable circuits

Abstract

Presented is a low supply voltage oscillator circuit having at least one capacitor to be controlled, connected between first and second voltage references, and a circuit for charging and discharging the capacitor to be controlled. The oscillator circuit also includes at least first and second stages having symmetrical structures in a mirror-image configuration and being connected between the first voltage reference and the second voltage reference and connected together through a memory element. The oscillator circuit also includes respective primary switches for alternately charging the capacitors in a controlled fashion.

Claims

1. A low supply voltage oscillator circuit comprising:

a first capacitor and a second capacitor to be controlled, each connected between first and second voltage references; and

a circuit for charging and discharging said capacitors to be controlled, including;

at least first and second stages having symmetrical structures in a mirror-image configuration and being connected between the first voltage reference and the second voltage reference;

a memory element that connects the first and second stages together and has first and second inputs;

first and second primary switches for alternately charging in a controlled fashion said capacitors, the first and second primary switches being connected respectively to the first and second capacitors at first and second connection nodes, respectively; and

first and second secondary switches coupled respectively between the second voltage reference and the first and second inputs of the memory element, the first secondary switch having a control terminal coupled to the first connection node, and the second secondary switch having a control terminal coupled to the second connection node.

2. The low supply voltage oscillator circuit according to claim 1 wherein said memory element is a flip-flop having a first input terminal connected to said first stage, a second input terminal connected to said second stage, a first output terminal connected to a first output terminal of the oscillator circuit, and a second output terminal connected to a second output terminal of the oscillator circuit.

3. The low supply voltage oscillator circuit according to claim 2 wherein the circuit for charging and discharging includes a controlled supply circuit for said capacitors to be controlled, the controlled supply circuit including at least one current generating circuit and the first and second primary switches have respective control terminals coupled respectively to the first and second output terminals of the flip-flop.

4. The low supply voltage oscillator circuit according to claim 3 wherein said controlled supply circuit comprises first and second charge current generating circuits connected, in series with said first and second capacitors, respectively, between the first voltage reference and the second voltage reference.

5. The low supply voltage oscillator circuit according to claim 1, wherein said circuit for charging and discharging further includes first and second control current generating circuits respectively connected in series with the first and second secondary switches between the first voltage reference and the second voltage reference.

6. The low supply voltage oscillator circuit according to claim 1 wherein said circuit for charging and discharging includes a distributed current mirror comprising first, second, third, and fourth MOS transistors having respective source terminals connected to the first voltage reference and gate terminals jointly connected to a gate terminal of a fifth MOS transistor, which is diode connected between the first voltage reference and, through a bias current generator, the second voltage reference.

7. The low supply voltage oscillator circuit according to claim 6 wherein the base current generator comprises a first transistor and a resistive element connected in series with each other between the fifth MOS transistor and the second voltage reference, and a sixth MOS transistor connected in a current mirror configuration with the fifth MOS transistor between the first voltage reference and, through a seventh MOS transistor, the second voltage reference, thereby making the frequency of oscillation of the oscillator circuit independent of the threshold value V_TH of the MOS transistors entering its construction and dependent on the resistance of the resistive element.

8. The low supply voltage oscillator circuit according to claim 7 wherein said first transistor has a control terminal connected to an interconnection node between said sixth and seventh MOS transistors, the seventh MOS transistor having a control terminal connected to an interconnection node between the first transistor and the resistive element.

9. The low supply voltage oscillator circuit according to claim 5 wherein said primary and secondary switches comprise MOS transistors having source terminals connected to the second voltage reference.

10. The low supply voltage oscillator circuit according to claim 1, wherein said primary switches are resistive, so that a voltage pattern of triangular shape may be obtained at the capacitors to be controlled, particularly for low electromagnetic interference applications.

11. A low supply voltage oscillator circuit, comprising:

a first capacitor connected between first and second voltage references;

a first primary switch coupled to the first capacitor and structured to discharge a charge stored in the first capacitor when a control terminal of the first primary switch receives a first control signal;

a memory element having a first input and a first output coupled to the control terminal of the first primary switch, the memory element being structured to generate the first control signal at the first output based on a state at the first input; and

a current mirror circuit that includes;

a current generator;

a first mirror transistor connected with the current generator between the first and second voltage references;

a second mirror transistor connected with the first capacitor between the first and second voltage references and having a control terminal connected to a control terminal of the first mirror transistor; and

a third mirror transistor connected between the first voltage reference and the first input of the memory element and having a control terminal connected to the control terminal of the first mirror transistor.

12. The oscillator circuit of claim 11, further comprising a secondary switch coupled between the first input of the memory element and the second voltage reference, the secondary switch having a control terminal coupled to an interconnection node between the second mirror transistor and the first capacitor.

13. The oscillator circuit of claim 11 wherein the memory element includes a second output that supplies a second control signal, the oscillator circuit further comprising:

a second capacitor connected between the first and second voltage references;

a second primary switch coupled to the second capacitor and structured to discharge a charge stored in the second capacitor when a control terminal of the second primary switch receives the second control signal.

14. The oscillator circuit of claim 13 wherein the current mirror circuit includes a fourth mirror transistor connected between the first voltage reference and a second input of the memory element and having a control terminal connected to the control terminal of the first mirror transistor.

15. The oscillator circuit of claim 14 wherein the current mirror circuit includes a fifth mirror transistor coupled with the second capacitor between the first and second voltage references and having a control terminal connected to the control terminal of the first mirror transistor.

16. The oscillator circuit of claim 11 wherein the current generator includes:

a first transistor and a resistive element connected in series between the first mirror transistor and the second voltage reference;

a fourth mirror transistor connected in a current mirror configuration with the first mirror transistor; and

a second transistor connected with the fourth mirror transistor between the first and second voltage references.

17. The oscillator circuit of claim 16 wherein the first transistor has a control terminal connected to an interconnection node between the fourth mirror transistor and the second transistor, the second transistor having a control terminal connected to an interconnection node between the first transistor and the resistive element.