Write circuit for large MRAM arrays

• US 6,363,000 B2
• Filed: 04/05/2001
• Issued: 03/26/2002
• Est. Priority Date: 05/03/2000
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Tran, Lung T, Eldredge, Kenneth J, Perner, Frederick A
• Primary Examiner(s): Ho, Hoai V.
• Application Number:
  US09/827,114
• Publication Number:
  US 20010038548A1
• Time in Patent Office: 355 Days
• Field of Search: 365/173, 365/66, 365/230.06, 365/63, 365/129, 365/230.01
• US Class Current: 365/66
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect

Abstract

A write circuit for a large array of memory cells of a Magnetic Random Access Memory (“MRAM”) device. The write circuit can provide a controllable, bi-directional write current to selected word and bit lines without exceeding breakdown limits of the memory cells. Additionally, the write circuit can spread out the write currents over time to reduce peak currents.

Claims

1. A method of writing data to an array of memory cells, selected memory cells being crossed by a selected first line and different selected second lines, additional memory cells in the array being crossed by unselected lines, the method comprising the steps of:

supplying a first write current to the selected first line;

supplying a second write current to the selected second line; and

connecting both ends of the unselected lines to a high impedance.

2. An MRAM device comprising:

an array of memory cells;

a plurality of word lines crossing the memory cells;

a plurality of bit lines crossing the memory cells; and

a write circuit including a plurality of first and second switches for coupling first and second ends of unselected word lines to a high impedance during a write operation; and

a plurality of third and fourth switches for coupling first and second ends of unselected bit lines to a high impedance during a write operation.

3. A circuit for an MRAM device, the MRAM device including an array of memory cells, a plurality of bit lines crossing columns of the memory cells and a plurality of word lines crossing rows of the memory cells, the circuit comprising:

a plurality of first and second switches for coupling first and second ends of unselected word lines to a high impedance during a write operation; and

a plurality of third and fourth switches for coupling first and second ends of unselected bit lines to a high impedance during the write operation.

4. The circuit of claim 3, wherein one of the first switches applies a reference potential to the first end of a selected word line during a write operation;

wherein one of the second switches applies a row write potential to the second end of a selected word line during a write operation;

wherein one of the third switches applies one of a reference potential and a first column write potential to the first end of a selected bit line during a write operation; and

wherein one of the fourth switches applies one of a reference potential and the second column write potential to the second end of a selected bit line during a write operation.

5. The circuit of claim 4, further comprising a push-pull circuit for applying the write potentials to the third and fourth switches.

6. The circuit of claim 3, wherein the first and second switches are configured to supply a unidirectional write current to the word lines, and the third and fourth switches are configured to supply a bi-directional write current to the bit lines.

7. The circuit of claim 6, further comprising a single current source connected to the first switches.

8. The circuit of claim 3, wherein the third switches are part a slave driver and wherein the fourth switches are part of a master driver, the master and slave drivers applying bi-directional write currents to selected bit lines during a write operation.

9. The circuit of claim 8, wherein current is caused to flow in one direction by the slave driver connecting a selected bit line to a first write potential and the master driver connecting the selected bit line to a reference potential;

and wherein current is caused to flow in the opposite direction by the slave driver connecting the selected bit line to the reference potential and the master driver connecting the selected bit line to the second write potential.

10. The circuit of claim 8, further comprising sense amplifiers for the bit fines, the column driver connecting a first end of a selected bit line to the sense amplifier and master write driver during both read and write operations, connecting ends of unselected bit lines to a read potential during read operations, and connecting the ends of unselected bit lines to a high impedance during write operations.

11. The circuit of claim 3, wherein the second switches are part of row read/write drivers and the fourth switches are part of column R/W drivers, one of the row and column read/write drivers providing the same potential to unselected lines as a selected line during read operations.

12. A circuit for writing data to an array of memory cells, selected memory cells crossed by a selected first line and different selected second lines, additional memory cells in the array crossed by unselected lines, the circuit comprising:

switches for causing a first write current to flow through the selected first line and a second write current to flow through the selected second lines; and

means for connecting both ends of the unselected lines to a high impedance.

13. The circuit of claim 12, further comprising sense amplifiers for sensing logic states of selected memory cells;

the means coupling first ends of selected second lines to the sense amplifiers during read operations, the means connecting ends of subsets of unselected first and second lines to a read potential during the read operations.

14. The circuit of claim 13, further comprising sense amplifiers for the bit lines, a first end of each selected bit line being supplied with an operating potential during read operations, ends of a subset of unselected word and bit lines being supplied with an equal potential during read operations.