Multi-bit-cell non-volatile memory with maximized data capacity

• US 6,363,008 B1
• Filed: 02/17/2000
• Issued: 03/26/2002
• Est. Priority Date: 02/17/2000
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Multi Level Memory Technology
• Inventors: Wong, Sau-Ching
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US09/505,519
• Time in Patent Office: 768 Days
• Field of Search: 365/185.03, 365/189.05, 365/189.12, 365/230.03, 365/189.03
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A multiple-bit-per-cell memory includes multiple memory arrays, where the number of bits stored per cell is separately set for each of the memory arrays. Memory arrays that testing proves are accurate when writing, storing, and reading a larger number of bits per cell are set to store more bits per cell, and memory arrays that cannot accurately write, store, or read as many bits per cell are set to store fewer bits per cell. Accordingly, the setting of the numbers of bits per cell for the respective memory arrays can maximize the capacity of a memory when some arrays perform better than expected. When the memory arrays on average perform worse than expected, the setting of the numbers of bits per cell salvage the memory device even if the memory is unable to provide the total expected memory capacity. One implementation of the memory includes a register for the settings of the memory arrays and one or more analog/multi-level write and read circuits. One or more converters convert between the analog and digital signals where the digital signals contain a number of bits selected according to a memory array being accessed. A data buffer between the arrays and a data input/output interface collects data for conversion between the variable data sizes used in the memory and standard size data units input and output from the memory.

Claims

1. A memory comprising:

a plurality of memory arrays including a first memory array and a second memory array, the first memory array being configured to store N1 bits per memory cell, the second memory array being configured to store N2 bits per memory cell, where N2 is less than N1 and greater than zero;

a data input/output interface; and

a data buffer coupled between the input/output interface and the plurality of memory arrays, the data buffer collecting data read from or to be written to the plurality of memory cells.

2. The memory of claim 1, wherein:

for an operation reading from the first memory array, the data buffer collects N1 bits of data from each memory cell read for subsequent output through the input/output interface; and

for an operation reading from the second memory array, the data buffer collects N2 bits of data from each memory cell read for subsequent output through the input/output interface.

3. The memory of claim 1, wherein:

for an operation writing to the first memory array, the data buffer provides N1 bits of data for each memory cell to which data is being written; and

for an operation writing to the second memory array, the data buffer provides N2 bits of data for each memory cell to which data is being written.

4. The memory of claim 1, further comprising a register storing a plurality of values including N1 and N2, wherein each value stored in the register corresponds to one of the plurality of arrays and indicates a number bits stored per memory cell in the corresponding array.

5. The memory of claim 4, wherein the register is user-accessible for examination of the plurality of values.

6. The memory of claim 4, wherein the register is user-accessible for changing the plurality of values.

7. The memory of claim 4, wherein the register comprises non-volatile memory storing the plurality of values.

8. The memory of claim 1, further comprising a read circuit coupled to the second memory array, the read circuit generating an Nmax-bit value according to a threshold voltage of a selected memory cell in the second memory array, wherein Nmax is greater than N2.

9. A memory comprising:

a plurality of memory units, each memory unit comprising;

a memory array;

a write circuit that receives an Nmax-bit value and programs a threshold voltage of a memory cell in the array, to a target level selected according to the Nmax-bit value; and

a read circuit that generates an Nmax-bit value according to a threshold voltage of a memory cell being read;

a global data bus coupled to provide Nmax-bit values to the write circuits and receive Nmax-bit values from the read circuits; and

input/output circuitry coupled to the global data bus, the input/output circuitry selecting a number of bits on the global data bus that are actual data, the number of bits depending on which of the plurality of memory units is involved in a data transfer on the global data bus.

10. The memory of claim 9, further comprising a configuration register coupled to the input/output circuitry, the configuration register containing configuration values indicating for each memory unit, a number of data bits stored per memory cell in that memory unit.

11. The memory of claim 10 wherein the configuration register is user-accessible for examination of the configuration values.

12. The memory of claim 10 wherein the configuration register is user-accessible for changing of the configuration values.

13. The memory of claim 10, wherein the configuration register comprises non-volatile memory storing the configuration values.

14. A memory comprising:

a plurality of memory units;

a global write/read circuit coupled to the plurality of memory units to control writing to and reading from the plurality of memory units;

input/output circuitry coupled to the global write/read circuit, the input/output circuitry selecting a number of bits of actual data transferred by a write or read operation, the number of bits depending on which of the plurality of memory units is the target of the write or read operation; and

a converter coupled to the global write/read circuit, wherein

the converter converts a first digital signal to an analog signal representing a value for a write operation that the global write/read circuit controls, the digital signal containing a number of data bits selected by the input/output circuitry; and

the converter converts an analog signal from the global write/read circuit to a second digital signal, the second digital signal containing a number of data bits selected by the input/output circuitry.

15. A memory comprising:

a plurality of memory units;

a global write/read circuit coupled to the plurality of memory units to control writing to and reading from the plurality of memory units;

input/output circuitry coupled to the global write/read circuit, the input/output circuitry selecting a number of bits of actual data transferred by a write or read operation, the number of bits depending on which of the plurality of memory units is the target of the write or read operation; and

a configuration register coupled to the input/output circuitry, the configuration register containing configuration values indicating for each memory unit, a number of data bits stored per memory cell in that memory unit.

16. The memory of claim 15 wherein the configuration register is user-accessible for examination of the configuration values.

17. The memory of claim 15 wherein the configuration register is user-accessible for changing of the configuration values.

18. The memory of claim 15, wherein the configuration register comprises non-volatile memory storing the configuration values.

19. A method for using an integrated circuit memory, comprising:

selecting a first memory array in the integrated circuit memory;

identifying a number N1 of bits per cell for the first memory array;

accessing a first selected memory cell in the first memory array, wherein the access of the first selected memory cell transfers N1 bits of data;

selecting a second memory array in the integrated circuit memory;

identifying a number N2 of bits per cell for the second memory array, wherein N2 differs from N1; and

accessing a second selected memory cell in the second memory array, wherein the access of the second selected memory cell transfers N2 bits of data.

20. The method of claim 19, wherein:

identifying the number N1 comprises reading the number N1 from a first register entry that corresponds to the first memory array; and

identifying the number N2 comprises reading the number N2 from a second register entry that corresponds to the second memory array.

21. The method of claim 20, wherein the first and second register entries are in a volatile memory.

22. The method of claim 21, further comprising a start-up procedure for the memory, the start-up procedure comprising:

reading the values N1 and N2 from non-volatile memory; and

storing the numbers N1 and N2 in the volatile memory.

23. The method of claim 21, a user writing the numbers N1 and N2 to the volatile memory to select a storage density for the first and second memory units.

24. The method of claim 19, wherein:

accessing the first selected memory cell comprises reading the first selected memory cell to determine an N1-bit value that corresponds to a threshold voltage of the first selected memory cell; and

accessing the second selected memory cell comprises reading the second selected memory cell to determine an N2-bit value that corresponds to a threshold voltage of the second selected memory cell.

25. The method of claim 19, wherein:

accessing the first selected memory cell comprises writing to the first selected memory cell to set a threshold voltage of the first selected memory cell to a level corresponding to an N1-bit value; and

accessing the second selected memory cell comprises writing to the second selected memory cell to set a threshold voltage of the second selected memory cell to a level corresponding to an N2-bit value.

26. A method for using a non-volatile integrated circuit memory, comprising:

configuring the non-volatile integrated circuit memory by writing a value N1 in a first register entry corresponding to a first memory unit in the non-volatile integrated circuit memory; and

accessing a first selected memory cell in the first memory unit, wherein the value N1 indicates a number of data bits that the access transfers to or from the first selected memory cell.

27. The method of claim 26, further comprising:

writing a value N2 in a second register entry corresponding to a second memory unit in the non-volatile integrated circuit memory; and

accessing a second selected memory cell in the second memory unit, wherein the access of the second selected memory cell transfers N2 bits of data.

28. The method of claim 27, wherein N2 differs from N1.

29. The method of claim 26, wherein the configuring is performed during a start-up procedure for the non-volatile integrated circuit memory.

30. The method of claim 26, wherein the configuring is performed by inputting a signal that represents the value N1, into the non-volatile integrated circuit memory.