Control channel determiner

• US 6,363,055 B1
• Filed: 07/07/1997
• Issued: 03/26/2002
• Est. Priority Date: 05/06/1997
• Status: Expired due to Term

• Current Assignee: ST-Ericcson SA (Telefonaktiebolaget LM Ericsson)
• Original Assignee: DSPC Technologies Limited
• Inventors: Sasson, Roni
• Primary Examiner(s): NGO, RICKY QUOC
• Application Number:
  US08/889,308
• Time in Patent Office: 1,723 Days
• Field of Search: 370/252, 370/242, 370/247, 370/345, 370/347, 370/348, 370/349, 370/350, 370/442, 370/443, 370/458, 370/459, 370/470, 370/471, 370/472, 370/337, 371/31, 371/67.1, 371/68.1, 371/68.2
• US Class Current: 370/252
• CPC Class Codes: H04J 3/0608 Detectors therefor, e.g. correlators, state machines

Abstract

A unit for determining whether or not a received channel is a control channel is provided. The unit includes a superframe phase estimator and a state machine. The superframe phase estimator estimates the superframe phase based on elapsed time. The state machine determines the validity and the value of a decoded superframe phase field of a received time slot based on the quality of the decoding and in comparison to the estimated superframe phase. The state machine also initializes the superframe estimator.

Claims

1. A state machine comprising:

a first set of at least one logic device configured to produce an invalid state to indicate that a valid superframe phase field is not present, a second set of at least one logic device configured to produce a between state to indicate that synchronization to a superframe phase field is in progress, and a third set of at least one logic device configured to produce a valid state to indicate that a valid superframe phase field is present, wherein first, second and third sets may overlap.

2. The state machine according to claim 1 and wherein said invalid state is achievable upon synchronization to a new channel or if said superframe phase field has not matched an estimated superframe phase value for a predetermined number N1 of time slots.

3. The state machine according to claim 1, and wherein said between state is achievable after being in said invalid state if said superframe phase field has been correctly received for a predetermined number N2 of time slots or upon return from a short sleep not requiring synchronization to a new channel.

4. The state machine according to claim 2 and wherein said valid state is achievable if said superframe phase field has been equal to said estimated superframe value for a predetermined number N3 of time slots.

5. The state machine according to claim 2 and wherein said state machine moves from said valid state to said between state or from said between state to said invalid state if said superframe phase field has not matched said estimated superframe value for predetermined numbers N4 and N5 of time slots, respectively.

6. Apparatus comprising:

a superframe phase estimator adapted to estimate the superframe phase based on elapsed time; and

a state machine having an invalid state, a between state and a valid state wherein

said invalid state is adapted to indicate that a valid superframe phase field is not present,

said between state is adapted to indicate that synchronization to a superframe phase field is in progress, and

said valid state is adapted to indicate that a valid superframe phase field is present.

7. The apparatus according to claim 6, wherein said invalid state is achievable upon synchronization to a new channel or if said superframe phase field has not matched an estimated superframe phase value for a predetermined number N1 of time slots.

8. The apparatus according to claim 6, wherein said between state is achievable after being in said invalid state if said superframe phase field has been correctly received for a predetermined number N2 of time slots or upon return from a short sleep not requiring synchronization to a new channel.

9. The apparatus according to claim 6 and wherein said valid state is achievable if said superframe phase field has been equal to said estimated superframe value for a predetermined number N3 of time slots.

10. The apparatus according to claim 6, wherein said state machine moves from said valid state to said between state or from said between state to said invalid state if said superframe phase field has not matched said estimated superframe value for predetermined numbers N4 and N5 of time slots, respectively.

11. The apparatus according to claim 6 and wherein said superframe phase estimator is a counter which increments by a predetermined amount every time slot during active operation and by the amount of time slots lapsed during a sleep time.