Exponential calculation device and decoding device

• US 6,363,407 B1
• Filed: 08/14/2001
• Issued: 03/26/2002
• Est. Priority Date: 02/04/1998
• Status: Expired due to Term

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Nishio, Kosuke, Sueyoshi, Masahiro, Katayama, Takashi, Fujita, Takeshi, Kawamura, Akihisa, Miyasaka, Shuji, Matsumoto, Masaharu, Abe, Kazutaka
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US09/929,156
• Publication Number:
  US 20020032712A1
• Time in Patent Office: 224 Days
• Field of Search: 708/606, 708/512, 708/517, 708/491
• US Class Current: 708/606
• CPC Class Codes: G06F 7/552 Powers or roots , e.g. Pythagorean sums
• CPC Class Codes: G10L 19/0212 using orthogonal transformation

Abstract

A device of the present invention is an exponential calculation device for calculating x{circumflex over ( )}(a/b) (where a and b are each an integer constant) for a given input value of x. The device includes: an input control section for outputting a value of x′, wherein x′=x when x≦A (where A is a threshold value within a variable range of x) and x′=x/2{circumflex over ( )}b when x>A; a core section for outputting a value of z′=x′{circumflex over ( )}(a/b); and an output control section for outputting a value of z, wherein z=z′ when x≦A and z=z′*2{circumflex over ( )}a when x>A.

Claims

1. A decoding device for extracting a variable quantization code x and a variable scaling factor y from an input bit stream containing the quantization code x and the scaling factor y and calculating x{circumflex over ( )}(a/b)*2{circumflex over ( )}(y/c) (where a, b and c are each an integer constant), the device comprising:

an isolation section for isolating x and y from the input bit stream;

a first bit shift section for, when x≦

2{circumflex over ( )}N (where N is a predetermined threshold value), shifting x by a number of bits according to N so as to convert x to x1 which is in a fixed point format;

a first memory section for storing, for all possible values of q (where q is an integer such that 0≦

q≦

2{circumflex over ( )}N), using q as an address, values of H(q) which have been converted to a fixed point format by shifting q{circumflex over ( )}((a−

b)/b) by a number of bits according to M (where M is an integer value of (N*(a−

b))/b);

a second memory section for storing, for all possible values of p (where 0≦

p<

c), values of G(p)=2{circumflex over ( )}(p/c) in a fixed point format;

a division section for calculating y1, where y1=int(y/c);

a modulo calculation section for calculating y2=y%c;

a multiplication section for outputting a value obtained by multiplying together a value of H(x) which has been read out from the first memory section using x as an address, a value of G(y2) which has been read out from the second memory section using y2 as an address and a value of x1 which has been converted by the first bit shift section; and

a second bit shift section for shifting the output value from the multiplication section by a number of bits according to y1 obtained by the division section.

2. A decoding device according to claim 1, wherein:

the number of bits according to N is (D−

N) (where D is a number of significant digits of a fractional portion of a number involved in a fixed point calculation operation); and

the number of bits according to y1 is (y1+(N+M)).

3. A decoding device according to claim 1, wherein:

M is an integer obtained by rounding up (N*(a−

b))/b.

4. A decoding device according to claim 1, wherein a=4, b=3 and c=4.

5. A decoding device according to claim 1, further comprising:

a determination section for outputting a determination result being true when x≦

2{circumflex over ( )}N and being false when x>

2{circumflex over ( )}N; and

a second division section for outputting the value of x without alteration when the determination result is true and for outputting a value obtained by dividing x by (2{circumflex over ( )}(b*i)), wherein;

the first bit shift section shifts x by a number of bits according to (N+b*i) (where i is an integer which is not negative) when the determination result is false;

the first memory section stores values of H(q) for values of q which are within the variable range of x; and

the second bit shift section shifts the value output from the multiplication section by a number of bits according to y1 when the determination result is true and by a number of bits according to y1 and a*i when the determination result is false.

6. A decoding device according to claim 5, wherein:

the number of bits according to N is (D−

N);

the number of bits according to (N+b*i) is D−

(N+b*i);

the number of bits according to M is (D−

M);

the number of bits according to y1 is (y1+N+M); and

the number of bits according to y1 and a*i is (y1+N+M+a*i).

7. A decoding device according to claim 5, wherein the value of i is determined so that x satisfies 2{circumflex over ( )}(N+b(i−

1))<

x≦

2{circumflex over ( )}(N+bi).

8. A decoding device according to claim 5, further comprising a determination section for outputting a determination result being true when x≦

2{circumflex over ( )}N and being false when x>

2{circumflex over ( )}N, and further outputting a parameter i for specifying a value of x, wherein;

the first bit shift section and the second division section and the second shifting section operate according to the determination result from the determination section.

9. A decoding device according to claim 8, wherein the second bit shift section shifts the value output from the multiplication section by a number of bits according to y1 when the determination result is true and by a number of bits according to y1+(a*i) when the determination result is false.

10. A decoding device for extracting a variable quantization code x and a variable scaling factor y from an input bit stream containing the quantization code x and the scaling factor y and calculating x{circumflex over ( )}(a/b)*2{circumflex over ( )}(y/c) (where a, b and c are each an integer constant), the device comprising:

an isolation section for isolating x and y from the input bit stream;

a determination section for outputting a determination result being true when x≦

2{circumflex over ( )}N (where N is a predetermined threshold value) and being false when x>

2{circumflex over ( )}N, and further outputting a parameter j for specifying a value of x;

a first bit shift section for shifting x by a number of bits according to N when the determination result is true and by a number of bits according to (N+j) when the determination result is false so as to convert x to x1 which is in a fixed point format;

a first division section for calculating y1, where y1=int(y/c);

a second division section for outputting a value of x′

, wherein x′

=x when the determination result is true and x′

is an integer value of (x/(2{circumflex over ( )}j));

a first memory section for storing, for all possible values of q{circumflex over ( )}(where q is an integer such that 0≦

q≦

2{circumflex over ( )}N) within a variable range of x′

, using q as an address, values of H(q) which have been converted to a fixed point format by shifting q{circumflex over ( )}((a−

b)/b) by a number of bits according to M (where M is an integer value of (N*(a−

b))/b);

an adjustment coefficient generation section for generating values of I(p,j) in a fixed point format according to 2{circumflex over ( )}(p/c)*2{circumflex over ( )}(j/b) for all possible values of p such that 0≦

p<

c and all possible values of j;

a modulo calculation section for calculating y2=y%c;

a multiplication section for outputting a value obtained by multiplying together a value of H(x′

) which has been read out from the first memory section using x′

as an address, a value of I(y2,j) corresponding to y2 and j which has been generated by the adjustment coefficient generation section and a value of x1 which has been converted by the first bit shift section; and

a second bit shift section for shifting the output value from the multiplication section by a number of bits according to y1 when x≦

2{circumflex over ( )}N and by a number of bits according to y1 and j when x>

2{circumflex over ( )}N.

11. A decoding device according to claim 10, wherein the adjustment coefficient generation section includes a second memory section for storing values of I(p,j) using p and j as an address.

12. A decoding device according to claim 10, wherein the value of j is determined so as to satisfy 2{circumflex over ( )}(N+(j−

1)<

x≦

2{circumflex over ( )}(N+j) when x>

2{circumflex over ( )}N, whereas j=0 when x≦

2{circumflex over ( )}N.

13. A decoding device according to claim 10, wherein a=4, b=3 and c=4.

14. A decoding device for extracting a variable quantization code x and a variable scaling factor y from an input bit stream containing the quantization code x and the scaling factor y and calculating x{circumflex over ( )}(a/b)*2{circumflex over ( )}(y/c) (where a, b and c are each an integer constant), the device comprising:

an isolation section for isolating x and y from the input bit stream;

a determination section for determining a number k of digits of x represented in a binary form;

a second division section for outputting a value of x′

, wherein the value of x′

is obtained by shifting x up by (N−

k) bits when the value of (N−

k) is positive and by shifting x down by (k−

N) bits when the value of (N−

k) is negative;

a first bit shift section for shifting x by a number of bits according to k so as to convert x to x1 which is in a fixed point format;

a first division section for calculating y1, where y1=int(y/c);

a first memory section for storing, using at least lower (N−

1) bits of q (where q is an integer such that 2{circumflex over ( )}(N−

1)≦

q<

2{circumflex over ( )}N) as an address, values of H(q) which have been converted to a fixed point format by shifting q{circumflex over ( )}((a−

b)/b) by a number of bits according to M (where M is an integer value of (N*(a−

b))/b);

an adjustment coefficient generation section for generating values of I(p,k) in a fixed point format according to 2{circumflex over ( )}(p/c)*2{circumflex over ( )}((k−

N)/b) for all possible values of p such that 0≦

p<

c and all possible values of k;

a modulo calculation section for calculating y2=y%c;

a multiplication section for outputting a value obtained by multiplying together a value of H(x′

) which has been read out from the first memory section using the at least lower (N−

1) bits of x′

as an address, a value of I(y2,k) corresponding to y2 and k which has been generated by the adjustment coefficient generation section and a value of x1 which has been converted by the first bit shift section; and

a second bit shift section for shifting the output value from the multiplication section by a number of bits according to y1, M and k.

15. A decoding device according to claim 14, wherein the adjustment coefficient generation section includes a second memory section for storing values of I(p,k) using p and k as an address.

16. A decoding device according to claim 14, wherein a=4, b=3 and c=4.