Memory system having flexible architecture and method
First Claim
1. A memory device, comprising:
- an array of memory cells;
a control register block for storing a plurality of control parameters;
control register modification circuitry operably coupled to the control register block and configured to reset at least some of a number of control registers in the control register block, addressing circuitry operably coupled to the array; and
memory operation circuity operably coupled to the control register block and to the array, said memory operation circuitry being configured to;
initiate memory program operations on the array when a first group of the control parameters are present in the control register block and terminate the memory program operations when a second group of the control parameters are present in the control register block;
initiate memory read operations on the array when a third group of the control parameters are present in the control register block and terminate that memory read operations when a fourth group of control parameters are present in the control register block; and
initiate an erase operation on the array when a fifth group of control parameters are present in the control register block and terminate the erase operation when a sixth group of control parameters are present in the control register block.
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Accused Products
Abstract
A memory system having a single memory controller connected to several memory devices by way of a common bus, with the memory controller configured to issue memory program, memory read and memory erase instructions over the system bus to a selected one of the memory devices. Each memory device has an array of memory cells and several volatile control registers which contain control parameters provided by the memory controller. The control parameters operate to control one or more of the voltages applied to the array in memory read, program and erase operations, including the timing of the application of the voltages and the magnitude of the voltages so that the memory operations can be optimized by the memory controller.
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Citations
105 Claims
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1. A memory device, comprising:
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an array of memory cells;
a control register block for storing a plurality of control parameters;
control register modification circuitry operably coupled to the control register block and configured to reset at least some of a number of control registers in the control register block, addressing circuitry operably coupled to the array; and
memory operation circuity operably coupled to the control register block and to the array, said memory operation circuitry being configured to;
initiate memory program operations on the array when a first group of the control parameters are present in the control register block and terminate the memory program operations when a second group of the control parameters are present in the control register block;
initiate memory read operations on the array when a third group of the control parameters are present in the control register block and terminate that memory read operations when a fourth group of control parameters are present in the control register block; and
initiate an erase operation on the array when a fifth group of control parameters are present in the control register block and terminate the erase operation when a sixth group of control parameters are present in the control register block. - View Dependent Claims (2)
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3. A memory system comprising:
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a system bus;
a memory controller coupled to the system bus, with said memory controller being configured to issue memory program instructions and memory read instructions over the system bus; and
at least one memory device coupled to the system bus, with the memory device comprising;
an array of memory cells;
a control register block having a plurality of control registers for storing a plurality of control parameters;
control register modification circuitry operably coupled to the control register block and configured to modify the control parameters in response to memory instructions;
addressing circuitry operably coupled to the array; and
a memory operation manager coupled to the system bus, to the array and to the control registers, said memory operation manager being configured to;
initiate memory program operations on the array when a first group of the control parameters are present in the control register block and terminate the memory program operations when a second group of the control parameters are present in the control register block;
initiate memory read operations on the array when a third group of the control parameters are present in the control register block and terminate the memory read operations when a fourth group of control parameters are present in the control register block; and
initiate an erase operation on the array when a fifth group of control parameters are present in the control register block and terminate the erase operation when a sixth group of control parameters are present in the control register block. - View Dependent Claims (4, 5, 6, 7, 8, 9, 10, 11)
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12. A memory system comprising:
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a system bus;
a memory controller coupled to the system bus, with said memory controller being configured to issue memory program instructions and memory read instructions over the system bus; and
at least one memory device coupled to the system bus, with the memory device comprising;
an array of memory cells;
a plurality of volatile control registers which contain control parameters set by the memory instructions provided by the memory controller; and
a memory operation manager coupled to the system bus, to the array and to the control registers, said memory operation manager being configured to receive the memory instructions over the system bus and to carry out memory read and program operations by applying operation voltages to the array, with at least one of the operation voltages being controlled by at least a first one of the control parameters;
wherein the cells include a drain, a source and a control gate and wherein the operation voltages include a read voltage applied to the control gate of at least one of the cells in the memory read operation and wherein the control parameters include at least two control parameter bits which control a magnitude of the read voltage; and
wherein the operations voltage include a first program voltage applied to the drains of at least one of the cells in the memory program operation and wherein the control parameters includes at least two control parameter bits which control a magnitude of the first program voltage. - View Dependent Claims (13, 14, 15, 16)
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17. A memory system comprising:
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a system bus;
a memory controller coupled to the system bus, with said memory controller being configured to issue memory instruction over the system bus;
at least one memory device coupled to the system bus, with the memory device comprising an array of memory cells; and
a plurality of volatile control registers which contain control parameters which are set by the memory instructions from the memory controller; and
a memory operation manager coupled to the system bus, to the array and to the control registers, said memory operation manager being configured to carry out memory program and read operations in response to the control parameters stored in the control registers, with the memory instructions including a program state command which sets a state of the control parameters such that at least one program operation voltage is applied to the array and a program stop command which sets a state of the control parameters such that the program operation voltage is removed from the array;
wherein the memory operations manager is further configured to configure a magnitude of the at least one program voltage in response to the control parameters; and
wherein the cells include a drain, a source and a control gate and wherein the at least one program voltage includes a first program voltage applied to the drain of the at least one cell and a second program voltage applied to the control gate of the at least one cell and wherein at least two of the control parameters determine a magnitude of the first program voltage and at least two of the control parameters determine a magnitude of the second program voltage. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25)
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26. A memory system comprising:
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a system bus which includes a tag bus and a data bus;
a memory controller coupled to the system bus, with said memory controller being configured to issue memory program instructions, memory read instructions, memory erase instructions and control register write instructions over the system bus, with the control register write instructions including control register write data; and
a plurality of memory devices coupled to the system bus and separate from one another and from the memory controller, with each of the memory devices comprising an array of non-volatile memory cells having control gates connected to common word lines, drains connected to common bit lines and at least one source line;
a plurality of volatile control registers; and
a memory operation manager coupled to the system bus, to the array and to the control registers, said memory operation manager being configured to receive the control register write instructions over the system bus and to transfer the control register write data to the control registers and to carry out memory read, program and erase operations using the control register write data in the control registers, the memory operations manager including voltage control circuitry;
wherein the voltage control circuitry is configured to switch to a low power consumption state when the control register controlling the circuitry is reset;
wherein each control register has an associated register address and wherein the memory controller is further configured to issue control register select instructions over the system bus, with the control register select instructions including one of the control register addresses and wherein the memory operation manager is further con figured to select one of the control registers based upon the control register address received on the system bus and to transfer the control register write data to the selected one of the control registers;
wherein the control register select instructions include a control register select command and wherein the memory controller is configured to transfer the control register select command over the tag bus and the control register address over the data bus and wherein the memory operation manager further comprises a command decoder configured to decode commands of the system bus with the command decoder, in response to detection of the control register select command, causing the control register having an address which corresponds to the control register address received on the data bus to be selected; and
wherein the voltage control circuitry is configured to apply voltages to the word lines, the bit lines and the at least one source line;
during the memory program, road and erase operations wherein the voltage control circuitry is controlled by at least one of the control registers.- View Dependent Claims (27)
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28. A memory system comprising:
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a system bus;
a memory controller coupled to the system bus, with said memory controller being configured to issue memory program instructions, memory read instructions, memory erase instructions and control register write instructions over the system bus, with the control register write instructions including control register write data; and
a plurality of memory devices coupled to the system bus and separate from one another and from the memory controller, with each of the memory devices comprising an array of non-volatile memory cells having control gates connected to common word lines, drains connected to common bit lines and sources connected to at least one source line;
a plurality of volatile control registers; and
a memory operation manager coupled to the system bus, to the array and to the control registers, said memory operation manager being configured to receive the control register write instructions over the system bus and to transfer the control register write data to the control registers and to carry out memory read, program and erase operations using voltage control circuitry configure to apply voltages to the word lines, bit lines and at least one source line, with the control register write data operating to control a magnitude of at least one voltage applied to the array during the memory operations by the voltage control circuitry;
wherein the voltage control circuitry farther comprises a first voltage source configured to provide a first positive voltage relative to a circuit common of the memory device and wherein the control register write data operates to control a magnitude of the first positive voltage and comprises two first source magnitude control parameter bits. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50)
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51. A memory system comprising:
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a system bus;
a memory controller coupled to the system bus, with said memory controller being configured to issue memory program instructions, memory read instructions and control register write instructions over the system bus, with the control register write instructions including control register write data; and
at least one memory device coupled to the system bus, with the memory device comprising;
an array of memory cells;
a plurality of volatile control registers; and
a memory operation manager coupled to the system bus, to the array and to the control registers, said memory operation manager being configured to receive the control register write instructions over the system bus and to transfer the control register write data to the control registers and to carry out memory read and program operations, with the memory operation manager comprising read array circuitry used in the memory read operations, with the read array circuitry comprising a plurality of sense amplifiers each of which includes a first input coupled to the array and a second input to be coupled to a compare voltage, with the control register write data operating to control a magnitude of the compare voltage;
wherein the read array circuitry comprises a reference voltage generator circuit which provides a reference voltage from which the compare voltage is derived and wherein the control register write data operates to control a magnitude of the reference voltage and comprises two reference generator magnitude control parameter bits. - View Dependent Claims (52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68)
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69. A memory system comprising:
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a system bus;
a memory controller coupled to the system bus, with said memory controller being configured to issue memory program instructions, memory read instructions and control register write instructions over the system bus, with the control register write instructions including control register write data; and
at least one memory device coupled to the system bus, with the memory device comprising;
an array of memory cells;
a plurality of volatile control registers; and
a memory operation manager coupled to the system bus, to the array and to the control registers, said memory operation manager being configured to receive the control register write instructions over the system bus and to transfer the control register write data to the control registers and to carry out memory read and program operations, with the memory operation manager comprising read array circuitry used in the memory read operations, with the read array circuitry comprising a plurality of sense amplifiers each of which includes a first input coupled to the array and a second input to be coupled to a compare voltage, with the control register write data operating to control a magnitude of the compare voltage;
wherein the memory cells are volatile memory cells and wherein the memory controller is further configured to carry out memory erase instructions and the operation manager is further configured to carry out memory erase operations by applying at least one erase voltage to the array, with the erase voltage having a magnitude controlled by at least two erase magnitude control parameter bits.
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70. A memory device for use in a memory system which comprises a memory controller and at least one of the memory devices coupled to the memory controller by way of a system bus, with the memory controller being configured to issue memory program instructions, memory read instructions, and control register write instructions over the system bus, with the control register write instruction including control register write data, said memory device comprising:
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an array of memory cells;
a plurality of volatile control registers;
read array circuitry which includes a plurality of sense amplifiers, each of which includes a first input coupled to the array and a second input coupled to a compare voltage, with the control register write data operating to control a magnitude of the compare voltage; and
a memory operation manager coupled to the system bus, to the array and to the control registers, said memory operation manager being configured to receive the control register write instructions over the system bus and to transfer the control register write data to the control registers and to carry out memory read and program operations using voltage control circuitry configured to apply voltages to the array, with the control register write data operating to cause the voltage control circuitry to adjust a magnitude of a first voltage applied to the array during at least the memory read operations;
wherein the sense amplifiers are switchable between an operating state and a non-operating state, with the sense amplifiers consuming reduced power in the non-operating state. - View Dependent Claims (71, 72, 73, 74)
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75. A memory device for use in a flash memory system which comprises a memory controller and a plurality of the memory devices coupled to the memory controller by way of a system buts, with the memory controller being configured to issue memory program instructions, memory read instructions, memory erase instructions and control register write instructions over the system bus, with the control register write instruction including control register write data, said memory devices each comprising:
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an array of flash memory cells having control gates connected to common word lines, drains connected to common bit lines and sources connected to at least one source line;
a plurality of volatile control registers; and
a memory operation manager coupled to the system bus, to the array and to the control registers, said memory operation manager being configured to receive the control register write instructions over the system bus and to transfer the control register write data to the control registers and to carry out memory read, program and erase operations using voltage control circuitry configured to apply voltages to the word lines, bit lines and at least one source line, with the control register write data operating to cause the voltage control circuitry to adjust a magnitude of a first voltage applied to the word lines during at least the memory read operations and with the operation manager further comprising a read array circuitry which includes a plurality of sense amplifiers, each of which includes a first input coupled to one of the bit lines and a second input coupled to a compare voltage, with the control register write data further operating to control a magnitude of the compare voltage;
wherein the read array circuitry further comprises a reference voltage generator circuit which provides a reference voltage from which the compare voltage is device and wherein the control register write data comprises three reference generator magnitude control parameter bits. - View Dependent Claims (76)
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77. A memory system comprising:
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a system bus including a tag bus and a data bus;
a memory controller coupled to the system bus, with said memory controller being configure to issue memory operation instructions over the system bus, with the memory operations including memory read, program and erase operations and with the memory operation instructions including control register write instructions, with the control register write instructions including a control register select commanding transferred over the tag bus together with a control register address transferred over the data bus, a control register write command transferred over the tag bus together with control register write data over the data bus; and
at least one memory device coupled to the system bus, with the memory device comprising;
an array of non-volatile memory cells;
a plurality of volatile control registers, with each of the control registers having an associated one of the control register addresses; and
a memory operation manager coupled to the system bus, to the array and to the control registers, said memory operation manager being configured to receive one of the control register select commands over the tag bus and to receive the control register address over the data bus and to select one of the control registers based upon the received control register address and being further configured to receive one of the control register write commands over the tag bus and the control register write data over the data bus and to transfer the control register write data to the selected control register and to carry out at least one of the memory operations utilizing the control register write data in the selected control register;
wherein the control register write instructions further include a plurality of first control register address commands which are transferred over the tag bus together with the control register write data transferred over the data bus and wherein the memory operation manager is further configured to receive one of the first control register address commands and to transfer the control register write data to a selected one of the control registers based upon the first control register address command and independent of any of the control register select commands. - View Dependent Claims (78, 79, 80, 81, 82)
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83. A memory system comprising:
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a system bus including a tag bus mid a data bus;
a memory controller coupled to the system bus, with said memory controller being configured to issue memory operation instructions over the system bus, with the memory operations including memory read, program and erase operations and with the memory operation instructions including control register write instructions, with the control register write instructions including a plurality of first control register address commands to be transferred over the tag bus together with first control register write data transferred over the data bus; and
at least one memory device coupled to the system bus, the majority devices comprising;
an array of non-volatile memory cells;
a plurality of volatile control registers, with each of the control registers having an associated control register address; and
a memory operation manager coupled to the system bus, to the array and to the control registers, said memory operation manager being configured to receive one of the first control register address commands over the tag bus and to receive the first control register write data over the data bus and to select a first one of the control registers based upon the received first control register address command and being further configured to transfer the first control register write data to the selected first control register and to carry out at least one of the memory operations utilizing the first control register write data in the selected control register;
wherein the control register write instructions further comprises a plurality of second control register address command to be transferred over the tag bus together with second control register write data transferred over the data bus and wherein the memory operation manager being configured to receive one of the second control register address commands over the tag bus and to select a second one of the control registers based upon the received second control register address command and to transfer the second control register write data to the selected second one of the control registers, with the memory operations manager being further configured to carry out at least one of the memory operations utilizing the second control register write data in the selected second control register. - View Dependent Claims (84, 85)
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86. A memory device comprising:
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an array of memory cells;
a control register block for storing a plurality of control parameters;
control register modification circuitry operably coupled to the control register block and configured to modify the control parameters in response to memory instructions;
addressing circuitry operably coupled to the array; and
memory operation circuitry operably coupled to the control register block and to the array, said memory operation circuitry being configured to;
initiate memory program operations on the array when a first group of the control parameters are present in the control register block and terminate the memory program operations when a second group of the control parameters are present in the control register block;
initiate memory read operations on the array when a third group of the control parameters are present in the control register block and to terminate the memory read operations when a fourth group of control parameters are present in the control register block; and
initiate all erase operation on the array when a fifth group of control parameters are present in the control register block and terminate the erase operation when a sixth group of control parameters are present in the control register block. - View Dependent Claims (87, 88, 89)
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90. A method of controlling operation of a memory system which includes a plurality of memory devices together by a common system bus, with each of the memory devices including an array of flash memory cells having control gates connected to common word lines, drains connected to common bit lines and sources connected to at least one source line, a plurality of control registers and a the memory operation manager coupled to the system bus and to the array, said memory operation manager being configured to carry out memory write, program and erase operations on the array, said method comprising the following steps:
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selecting one of the memory devices by transferring select information over the system bus;
providing a memory array address to the selected memory device by transferring address information over the system bus;
applying a first word line voltage to a word line of the array of the selected memory device based upon the memory array address by transferring a first word line control parameter over the system bus;
applying a first bit line voltage to at least one bit line of the array of the selected memory device based upon the memory address by transferring a first bit line control parameter over the system bus, with the first bit line control parameter being different from the first word line control parameter;
reading at least one of the cells connected to the word line to which the first word line voltage is applied and connected to the bit line to which the first bit line voltage is applied thereby generating read data;
transferring the read data out of the memory device over the system bus;
removing, subsequent to said step of reading, the first word line voltage from the word line by transferring a second word line control parameter over the system bus; and
removing, subsequent to said step of reading, the first bit line voltage from the bit line by transferring a second bit line control parameter over the system bus. - View Dependent Claims (91, 92, 93, 94, 95, 96, 97, 98)
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99. A method of controlling operation of a memory system which includes a plurality of memory devices together by a common system bus, with each of the memory devices including an array of flash memory cells having control gates connected to common word lines, drains connected to common bit lines and sources connected to at least one source line, a plurality of control registers and a memory operation manager coupled to the system bus, to the array and to the control registers, said memory operation manager being configured to carry out memory write, program and erase operations on the array, said method comprising the following steps:
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selecting one of the memory devices by transferring select information over the system bus;
providing a memory array address to the selected memory device by transferring address information over the system bus;
providing memory program data to the selected memory device by transferring program data information over the system bus;
applying a first word line voltage to a word line of the array of the selected memory device based upon the memory array address by transferring a first word line control parameter over the system bus;
applying a first bit line voltage to at least one bit line of the array of the selected memory device based upon the memory address by transferring a first bit line control parameter over the system bus, with the first bit line control parameter being different from the first word line control parameter;
programming at least one of the cells connected to the word line to which the first word line voltage is applied and connected to the bit line to which the first bit line voltage is applied with the program data;
removing, subsequent to said step of programming, the first word line voltage from the word line by transferring a second word line control parameter over the system bus; and
removing, subsequent to said step of programming, the first bit line voltage from the bit line by transferring a second bit line control parameter over the system bus. - View Dependent Claims (100, 101)
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102. A method of controlling operation of memory device which includes an array of memory cells, a volatile control register block and a memory operation manager coupled to the array and to the control register block, said memory operation manager being configured to carry out memory read and program operations, said method comprising the following steps:
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forwarding a memory address to the memory device over a system bus;
staring the memory address in the control register block;
forwarding memory program data to the memory device over the system bus;
storing the memory program data in the control register block;
forwarding memory program start instructions over the system bus;
storing a first set of control parameters based upon the program start instruction in control register block;
initiating a program operation of the memory program data by applying a first program voltage to a drain of at least one cell, and a second program voltage to a control gate of at least one cell, and wherein at least two of the control parameters determine the magnitude of the first program voltage, and at least two of the control parameters determine the magnitude of the second program voltage with the application of the first and second program voltages being controlled by the first set of control parameters;
forwarding memory program stop instructions over the system bus;
storing a second set of control parameters based upon the program stop instructions in the control register block; and
terminating the program operation by removing the first and second program voltages from the array, with the removal of the voltages being controlled by the second set of control parameters. - View Dependent Claims (103, 104)
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105. A method of controlling operation of a memory device which includes an array of memory cells, having control gates connected to common word lines, drains connected to common bit lines and sources connected to at least one source line a volatile control register block and a memory operation manager coupled to the array and to the control register block, said memory operation manager being configured to carry out memory read and program operations, said method comprising the following steps:
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providing a memory array address to the memory device by transferring address information over the system bus;
applying a fist word line voltage to a word line of the array of the memory device based upon the memory any address by transferring a first word line control parameter over the system bus;
applying a first bit line voltage to at least one bit line of the array of the memory device based upon the memory address by transferring a first bit line control parameter over the system bus, with the first bit line control parameter being different from the first word line control parameter;
reading at least one of the cells connected to the word line to which the first word line voltage is applied and connected to the bit line to which the first bit line voltage is applied thereby generating read data;
transferring the read data out of the memory device over the system bus;
removing, subsequent to said step of reading, the first word line voltage from the word line by transferring a second word line control parameter over the system bus; and
removing, subsequent to said step of reading, the first bit line voltage from the bit line by transferring a second bit line control parameter over the system bus.
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Specification