Method and apparatus for protecting flash memory
First Claim
1. In a computer system having a processor, a system memory, a flash memory, a memory controller, an apparatus comprising:
- a memory address/window detector coupled to said processor, said memory controller, a first input of a first logic gate and a first input of a second logic gate, said first logic gate having an output coupled to said memory controller and a second input for receiving a system memory access enable signal;
a memory window control coupled to said system memory, said memory controller, said flash memory, said memory address/window detector, an output of a third logic gate and a first input of a fourth logic gate, said fourth logic gate having a second input for receiving a flash memory programming enable signal;
a system memory access enable register coupled to an output of said second logic gate, a second input of said first logic gate, and an input of said third logic gate, wherein said memory window control is only accessible when said system memory access enable register is set to disabled;
a flash memory programming enable register coupled to an output of said fourth logic gate; and
a flash memory programming circuit coupled to said flash memory programming enable register and said flash memory, wherein said flash memory programming enable register is disabled if said system memory access enable register is set to enabled.
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Accused Products
Abstract
In a computer system including a processor, a system memory, a flash memory, and a memory controller, memory address/window detector coupled to the processor, the memory controller, a first input of a OR logic gate and a first input of an AND gate. The OR logic gate has an output coupled to the memory controller and a second input for receiving a system memory access enable signal. Also included is a memory window control coupled to the system memory, the memory controller, the flash memory, the memory address/window detector, an output of a NOT logic gate and a first input of another AND logic gate. The additional AND logic gate has a second input for receiving a flash memory programming enable signal. A system memory access enable register is included and is coupled to an output of the first AND logic gate, a second input of the OR logic gate, and an input of the NOT logic gate. The memory window control is only accessible when the system memory access enable register is set to disabled. A flash memory programming enable register is included where it is coupled to an output of the additional AND logic gate. Also included is a flash memory programming circuit that is coupled to the flash memory programming enable register and the flash memory. The flash memory programming enable register is disabled if said system memory access enable register is enabled.
113 Citations
33 Claims
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1. In a computer system having a processor, a system memory, a flash memory, a memory controller, an apparatus comprising:
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a memory address/window detector coupled to said processor, said memory controller, a first input of a first logic gate and a first input of a second logic gate, said first logic gate having an output coupled to said memory controller and a second input for receiving a system memory access enable signal;
a memory window control coupled to said system memory, said memory controller, said flash memory, said memory address/window detector, an output of a third logic gate and a first input of a fourth logic gate, said fourth logic gate having a second input for receiving a flash memory programming enable signal;
a system memory access enable register coupled to an output of said second logic gate, a second input of said first logic gate, and an input of said third logic gate, wherein said memory window control is only accessible when said system memory access enable register is set to disabled;
a flash memory programming enable register coupled to an output of said fourth logic gate; and
a flash memory programming circuit coupled to said flash memory programming enable register and said flash memory, wherein said flash memory programming enable register is disabled if said system memory access enable register is set to enabled. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory controller comprising:
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a first input for receiving an access enable signal; and
logic for limiting access by an electronic device to a predetermined portion of a system memory by disabling the access enable signal, wherein if the predetermined portion is all of the system memory allowing the electronic device to only access a flash memory.- View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
a first package containing the logic and having the first input; and
a second package containing the system memory.
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15. The memory controller of claim 9, where the system memory is contained in a package that is coupled to the memory controller.
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16. The memory controller of claim 9, where the electronic device is a processor.
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17. A system comprising:
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a system memory containing a flash memory upgrade program, wherein said flash memory upgrade program contains a BIOS image;
a flash memory protection unit coupled to the system having a first input for receiving an access enable signal; and
logic for limiting access to the flash memory upgrade program by flash upgrade program contained in the system memory.- View Dependent Claims (18, 19, 20)
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21. A method comprising:
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writing a set of instructions to a non-volatile memory if the instructions comprise an authenticating digital signature. - View Dependent Claims (22, 23, 24, 25, 26)
loading a base register with a starting address; and
loading a limit register with a value corresponding to the length of the set of instructions.
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25. The method of claim 21, further comprising loading the set of instructions into a system memory.
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26. The method of claim 21, wherein writing a set of instructions to a non-volatile memory includes writing the set of instructions to a memory comprising flash memory.
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27. An apparatus comprising:
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a processor;
a non-volatile memory coupled to the processor;
a system memory coupled to the processor to store a set of instructions; and
a memory controller adapted to write at least a portion of the set of instructions from the system memory to the non-volatile memory if the set of instructions comprise an authenticating digital signature. - View Dependent Claims (28, 29)
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30. An article comprising:
- a storage medium having stored thereon instructions, that, when executed by a computing platform, results in;
writing a set of instructions to a non-volatile memory if the instructions comprise an authenticating digital signature. - View Dependent Claims (31, 32, 33)
- a storage medium having stored thereon instructions, that, when executed by a computing platform, results in;
Specification