Method and apparatus for remotely evolving configuration bitstreams

• US 6,363,517 B1
• Filed: 06/17/1999
• Issued: 03/26/2002
• Est. Priority Date: 02/26/1999
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Levi, Delon, Guccione, Steven A.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US09/335,424
• Time in Patent Office: 1,013 Days
• Field of Search: 716/1-21, 709/201-203, 709/217-222, 713/1-2, 713/100
• US Class Current: 716/117
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06N 3/126 Evolutionary algorithms, e.g. genetic algorithms or genetic programming

Abstract

A system and method for evolving configuration bitstreams for a programmable logic device are disclosed. A plurality of data structures having respective sets of data are established. From the sets of data, respective configuration bitstreams are generated, wherein the sets of data are mapped to positions in the bitstreams. The configuration bitstreams are then evaluated for relative suitability to meet predetermined criteria when deployed on a programmable logic device. From the relative suitability of the configuration bitstreams, next-generation data for the data structures are generated using a genetic algorithm applied to sets of data. In the various embodiments, the configuration bitstreams eliminate resource contentions, selectively eliminate asynchronous behavior, include built-in test circuits, and are relocatable. Multiple populations of configuration bitstreams can evolve in parallel over a network.

Claims

1. A method for remotely evolving configuration bitstreams comprising the steps of:

at a remote site, providing;

an FPGA on which a design will operate; and

server software enabling the remote site to receive a bitstream, configure the FPGA, and send a readback bitstream;

at a local site;

generating a bitstream;

sending the bitstream to the remote site;

receiving the readback bitstream from the remote site; and

evaluating the readback bitstream.

2. The method of claim 1 wherein the readback bitstream provides data on states of registers in the FPGA.

3. The method of claim 1 wherein the readback bitstream provides a combination of the bitstream and state data from registers in the FPGA.

4. The method of claim 1 wherein the server software is XHWIF software available from Xilinx, Inc.