Fabrication of P-channel field effect transistor with minimized degradation of metal oxide gate

• US 6,365,450 B1
• Filed: 03/15/2001
• Issued: 04/02/2002
• Est. Priority Date: 03/15/2001
• Status: Expired due to Term

• Current Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Kim, Hyeon-Seag
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US09/809,706
• Time in Patent Office: 383 Days
• Field of Search: 438/216, 438/231, 438/232, 438/287, 438/305, 438/306, 438/655, 438/656, 438/785
• US Class Current: 438/216
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures

Abstract

For fabricating a PMOS (P-channel Metal Oxide Semiconductor) field effect transistor on a semiconductor substrate, a PMOS gate dielectric is formed on the semiconductor substrate, and a PMOS dummy gate electrode is formed on the gate dielectric. A P-type dopant is implanted into exposed regions of the semiconductor substrate to form a PMOS drain junction and a PMOS source junction. A thermal anneal is performed to activate the drain and source P-type dopant within the drain and source junctions. A PMOS drain silicide is formed with the drain junction, and a PMOS source silicide is formed with the source junction, in a silicidation process. An insulating material is deposited to surround the dummy gate electrode and the gate dielectric. The dummy gate electrode is etched away to form a PMOS gate electrode opening surrounded by the insulating material. The gate electrode opening is filled with a metal oxide material to form a PMOS metal oxide gate electrode after the thermal anneal process for activating the drain and source P-type dopant within the drain and source junctions and after the silicidation process for forming the drain and source silicides, to minimize degradation of the metal oxide gate electrode. In another aspect of the present invention, an insulating material is deposited on top of the metal oxide gate electrode to encapsulate the metal oxide gate electrode before performing a thermal anneal with hydrogen gas to prevent exposure of the metal oxide gate electrode to the hydrogen gas to further minimize degradation of the metal oxide gate electrode.

Claims

1. A method for fabricating a PMOS (P-channel Metal Oxide Semiconductor) field effect transistor on a semiconductor substrate, the method including the steps of:

A. depositing a layer of gate dielectric material on said semiconductor substrate;

B. depositing a layer of dummy gate electrode material on said layer of gate dielectric material;

C. patterning said layer of gate dielectric material and said layer of dummy gate electrode material over a first active device area of said semiconductor substrate to form a PMOS (P-channel Metal Oxide Semiconductor) gate dielectric from said gate dielectric material and to form a PMOS (P-channel Metal Oxide Semiconductor) dummy gate electrode from said dummy gate electrode material;

D. implanting a drain and source P-type dopant into exposed regions of said first active device area of said semiconductor substrate to form a PMOS (P-channel Metal Oxide Semiconductor) drain junction and a PMOS (P-channel Metal Oxide Semiconductor) source junction;

E. performing a thermal anneal to activate said drain and source P-type dopant within said PMOS drain and source junctions;

F. forming a PMOS (P-channel Metal Oxide Semiconductor) drain silicide with said PMOS drain junction and a PMOS (P-channel Metal Oxide Semiconductor) source silicide with said PMOS source junction;

G. depositing an insulating material to surround said PMOS dummy gate electrode and said PMOS gate dielectric;

H. etching away said PMOS dummy gate electrode to form a PMOS (P-channel Metal Oxide Semiconductor) gate electrode opening surrounded by said insulating material; and

I. filling said PMOS gate electrode opening with a metal oxide material to form a PMOS metal oxide gate electrode.

2. The method of claim 1, further including the steps of:

depositing an insulating material on top of said PMOS metal oxide gate electrode to encapsulate said PMOS metal oxide gate electrode; and

performing a thermal anneal with hydrogen gas after said PMOS metal oxide gate electrode is encapsulated to prevent exposure of said PMOS metal oxide gate electrode to hydrogen.

3. The method of claim 2, wherein said insulating material encapsulating said PMOS metal oxide gate electrode is comprised of silicon dioxide (SiO₂).

4. The method of claim 1, wherein said PMOS metal oxide gate electrode is comprised of one of ruthenium oxide (RuO₂) or iridium oxide (IrO₂).

5. The method of claim 1, wherein said gate dielectric material has a dielectric constant higher than that of silicon dioxide (SiO₂).

6. The method of claim 1, wherein said dummy gate electrode material is comprised of silicon nitride (Si₃N₄).

7. The method of claim 1, wherein said layer of gate dielectric material is comprised of a dummy gate dielectric material, and wherein said method further includes the steps of:

etching away said gate dielectric comprised of said dummy gate dielectric material at a bottom of said gate electrode opening such that said semiconductor substrate is exposed at the bottom of said gate electrode opening, after said step H and before said step I; and

depositing a gate dielectric material having a dielectric constant higher than that of silicon dioxide (SiO₂) on said semiconductor substrate at the bottom of said gate electrode opening to form said PMOS gate dielectric, before said step I.

8. The method of claim 7, wherein said dummy gate dielectric material is comprised of silicon dioxide (SiO₂).

9. The method of claim 1, further including the step of:

forming spacers comprised of an insulating material at sidewalls of said gate electrode opening before said step I.

10. The method of claim 1, wherein said step E of performing said thermal anneal to activate said drain and source P-type dopant within said PMOS drain and source junctions uses a temperature higher than about 1000°

Celsius.

11. The method of claim 1, wherein said step of forming said PMOS drain silicide and said PMOS source silicide uses a temperature higher than about 1000°

Celsius.

12. The method of claim 1, wherein said step G further includes the steps of:

conformally depositing said insulating material comprised of silicon dioxide (SiO₂) to cover said dummy gate electrode; and

polishing down said insulating material comprised of silicon dioxide (SiO₂) until said dummy gate electrode is exposed.

13. The method of claim 1, further including the steps of:

patterning said layer of gate dielectric material and said layer of dummy gate electrode material over a second active device area of said semiconductor substrate to form an NMOS (N-channel Metal Oxide Semiconductor) gate dielectric from said gate dielectric material and to form an NMOS (N-channel Metal Oxide Semiconductor) dummy gate electrode from said dummy gate electrode material;

implanting a drain and source N-type dopant into exposed regions of said second active device area of said semiconductor substrate to form an NMOS (N-channel Metal Oxide Semiconductor) drain junction and an NMOS (N-channel Metal Oxide Semiconductor) source junction;

performing a thermal anneal to activate said drain and source N-type dopant within said NMOS drain and source junctions before said step I;

forming an NMOS (N-channel Metal Oxide Semiconductor) drain silicide with said NMOS drain junction and an NMOS (N-channel Metal Oxide Semiconductor) source silicide with said NMOS source junction before said step I;

depositing an insulating material to surround said NMOS dummy gate electrode and said NMOS gate dielectric;

etching away said NMOS dummy gate electrode to form an NMOS (N-channel Metal Oxide Semiconductor) gate electrode opening surrounded by said insulating material; and

filling said NMOS gate electrode opening with a metal material to form an NMOS metal gate electrode.

14. The method of claim 13, wherein said NMOS metal gate electrode is comprised of one of aluminum, molybdenum, platinum, or tantalum.

15. A method for fabricating a PMOS (P-channel Metal Oxide Semiconductor) field effect transistor and an NMOS (N-channel Metal Oxide Semiconductor) field effect transistor on a semiconductor substrate, the method including the steps of:

A. depositing a layer of dummy gate dielectric material comprised of silicon dioxide (SiO₂) on said semiconductor substrate;

B. depositing a layer of dummy gate electrode material comprised of silicon nitride (Si₃N₄) on said layer of dummy gate dielectric material;

C. patterning said layer of dummy gate dielectric material and said layer of dummy gate electrode material over a first active device area of said semiconductor substrate to form a PMOS (P-channel Metal Oxide Semiconductor) dummy gate dielectric from said dummy gate dielectric material and to form a PMOS (P-channel Metal Oxide Semiconductor) dummy gate electrode from said dummy gate electrode material;

D. patterning said layer of dummy gate dielectric material and said layer of dummy gate electrode material over a second active device area of said semiconductor substrate to form an NMOS (N-channel Metal Oxide Semiconductor) dummy gate dielectric from said dummy gate dielectric material and to form an NMOS (N-channel Metal Oxide Semiconductor) dummy gate electrode from said dummy gate electrode material;

E. implanting a drain and source P-type dopant into exposed regions of said first active device area of said semiconductor substrate to form a PMOS (P-channel Metal Oxide Semiconductor) drain junction and a PMOS (P-channel Metal Oxide Semiconductor) source junction;

F. implanting a drain and source N-type dopant into exposed regions of said second active device area of said semiconductor substrate to form an NMOS (N-channel Metal Oxide Semiconductor) drain junction and an NMOS (N-channel Metal Oxide Semiconductor) source junction;

G. performing a thermal anneal using a temperature higher than about 1000°

Celsius to activate said drain and source P-type dopant within said PMOS drain and source junctions, and to active said drain and source N-type dopant within said NMOS drain and source junctions;

H. forming a PMOS (P-channel Metal Oxide Semiconductor) drain silicide with said PMOS drain junction and a PMOS (P-channel Metal Oxide Semiconductor) source silicide with said PMOS source junction, using a temperature higher than about 1000°

Celsius;

I. forming an NMOS (N-channel Metal Oxide Semiconductor) drain silicide with said NMOS drain junction and an NMOS (N-channel Metal Oxide Semiconductor) source silicide with said NMOS source junction, using a temperature higher than about 1000°

0 Celsius;

J. conformally depositing an insulating material comprised of silicon dioxide (SiO₂) to cover said PMOS dummy gate electrode and said PMOS dummy gate dielectric and to cover said NMOS dummy gate electrode and said NMOS dummy gate dielectric;

K. polishing down said insulating material comprised of silicon dioxide (SiO₂) until said PMOS dummy gate electrode and said NMOS dummy gate electrode are exposed;

L. etching away said PMOS dummy gate electrode to form a PMOS (P-channel Metal Oxide Semiconductor) gate electrode opening surrounded by said insulating material;

M. etching away said NMOS dummy gate electrode to form an NMOS (N-channel Metal Oxide Semiconductor) gate electrode opening surrounded by said insulating material;

N. etching away said PMOS dummy gate dielectric comprised of said dummy gate dielectric material at a bottom of said PMOS gate electrode opening such that said semiconductor substrate is exposed at the bottom of said PMOS gate electrode opening;

O. depositing a gate dielectric material having a dielectric constant higher than that of silicon dioxide (SiO₂) on said semiconductor substrate at the bottom of said PMOS gate electrode opening to form a PMOS gate dielectric;

P. etching away said NMOS dummy gate dielectric comprised of said dummy gate dielectric material at a bottom of said NMOS gate electrode opening such that said semiconductor substrate is exposed at the bottom of said NMOS gate electrode opening;

Q. depositing a gate dielectric material having a dielectric constant higher than that of silicon dioxide (SiO₂) on said semiconductor substrate at the bottom of said NMOS gate electrode opening to form an NMOS gate dielectric;

R. forming spacers comprised of silicon dioxide (SiO₂) at sidewalls of said PMOS gate electrode opening and at sidewalls of said NMOS gate electrode opening;

S. filling said PMOS gate electrode opening with a metal oxide material to form a PMOS metal oxide gate electrode;

wherein said PMOS metal oxide gate electrode is comprised of one of ruthenium oxide (RuO₂) or iridium oxide (IrO₂);

T. filling said NMOS gate electrode opening with a metal material to form an NMOS metal gate electrode;

wherein said NMOS metal gate electrode is comprised of one of aluminum, molybdenum, platinum, or tantalum;

U. depositing an insulating material comprised of silicon dioxide (SiO₂) on top of said PMOS metal oxide gate electrode and said NMOS metal gate electrode to encapsulate said PMOS metal oxide gate electrode and said NMOS metal gate electrode; and

V. performing a thermal anneal with hydrogen gas after said PMOS metal oxide gate electrode and said NMOS metal gate electrode are encapsulated to prevent exposure of said PMOS metal oxide gate electrode and said NMOS metal gate electrode to hydrogen.