Methods of forming power semiconductor devices having tapered trench-based insulating regions therein

• US 6,365,462 B2
• Filed: 11/29/2000
• Issued: 04/02/2002
• Est. Priority Date: 05/28/1999
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Micro-Ohm Corp. (ON Semiconductor Corporation)
• Inventors: Baliga, Bantval Jayant
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): NGUYEN, DILINH P
• Application Number:
  US09/726,088
• Publication Number:
  US 20010000033A1
• Time in Patent Office: 489 Days
• Field of Search: 438/589, 438/206, 438/216, 438/173, 438/133, 438/135, 438/738, 438/638-640, 438/689, 438/270-272, 438/700-703, 438/92, 438/167, 438/570, 438/259, 257/330, 257/333, 257/565
• US Class Current: 438/270
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

Power semiconductor devices having tapered insulating regions include a drift region of first conductivity type therein and first and second trenches in the substrate. The first and second trenches have first and second opposing sidewalls, respectively, that define a mesa therebetween into which the drift region extends. An electrically insulating region having tapered sidewalls is also provided in each of the trenches. The tapered thickness of each of the electrically insulating regions enhances the degree of uniformity of the electric field along the sidewalls of the trenches and in the mesa and allows the power device to support higher blocking voltages despite a high concentration of dopants in the drift region. In particular, an electrically insulating region lines the first sidewall of the first trench and has a nonuniform thickness T_ins(y) in a range between about 0.5 and 1.5 times T_ideal(Y), where T_ideal(y)|_y≧α=ε_ins((2ε_sE_cr/qW_mN_d)(y−α)+¼W_m)/ε_s and ε_ins is the permittivity of the electrically insulating region, ε_s is the permittivity of the drift region, E_cr is the breakdown electric field strength of the drift region, q is the electron charge, N_d is the first conductivity type doping concentration in the drift region, W_m is a width of the mesa, y is the depth, relative to a top of the first trench, at which the thickness of the electrically insulating region is being determined and α is a non-negative constant. The constant α may equal zero in the event the power device is a Schottky rectifier and may equal the depth of the P-base region/N-drift region junction in the event the power device is a vertical MOSFET.

Claims

1. A method of forming a power semiconductor device, comprising the steps of:

forming a trench in a semiconductor substrate;

lining a bottom and sidewalls of the trench with an electrically insulating layer;

then

filling the trench with a sacrificial electrically conductive region;

then

etching the electrically insulating layer at a first rate while simultaneously etching the sacrificial electrically conductive region at a second rate greater than the first rate, so that the electrically insulating layer has tapered sidewalls that extend outwardly, relative to the bottom of the trench, at an average slope of greater than about 500 Å

/μ

m relative to the sidewalls of the trench; and

then

refilling the trench with an electrically conductive electrode.

2. The method of claim 1, wherein the second rate is less than fifteen times greater than the first rate.

3. The method of claim 2, wherein said etching step comprises the step of etching all of the sacrificial electrically conductive region from the trench.

4. The method of claim 2, wherein the sacrificial electrically conductive region comprises polysilicon;

and wherein the electrically conductive electrode comprises polysilicon.

7. The method of claim 1, wherein the electrically insulating layer has tapered sidewalls and a uniformly thick bottom along the bottom of the trench.

5. A method of forming a power semiconductor device, comprising the steps of:

forming first and second trenches at a surface of a substrate having a drift region of first conductivity type therein, said first and second trenches having first and second sidewalls, respectively, that oppose each other and define a mesa therebetween into which the drift region extends;

lining the first trench with an electrically insulating layer;

then

covering the electrically insulating layer in the first trench by filling the first trench with a sacrificial electrically conductive region;

then

etching the electrically insulating layer at a first rate while simultaneously etching the sacrificial electrically conductive region at a second rate greater than the first rate, so that as the sacrificial electrically conductive region is etched at the second rate, additional portions of the electrically insulating layer are gradually exposed and etched at the first rate to obtain a nonuniformly thick electrically insulating layer, said nonuniformly thick electrically insulating layer having tapered sidewalls that extend outwardly, relative to the bottom of the trench, and a nonuniform thickness T_ins(y) in a range between about 0.5 and 1.5 times T_ideal(y), where;

6. The method of claim 5, wherein the electrically insulating layer has tapered sidewalls and a uniformly thick bottom along the bottom of the trench.