IC resistor and capacitor fabrication method

• US 6,365,480 B1
• Filed: 04/03/2001
• Issued: 04/02/2002
• Est. Priority Date: 11/27/2000
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Delaus, Michael D., Huppert, Gilbert L., Gleason, Edward
• Primary Examiner(s): Nguyen, Tuan H.
• Assistant Examiner(s): Huynh, Yennhu B.
• Application Number:
  US09/825,386
• Time in Patent Office: 364 Days
• Field of Search: 438/381, 438/382, 438/384, 438/240, 438/261, 438/329, 438/330, 438/385, 438/622, 438/706, 438/957, 438/656
• US Class Current: 438/381
• CPC Class Codes: H01L 27/0682 comprising combinations of capacitors and resistors
• CPC Class Codes: H01L 28/24 with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: Y10S 438/957 Making metal-insulator-metal device

Abstract

An IC resistor and capacitor fabrication method comprises depositing a dielectric layer over existing active devices and metal interconnections on an IC substrate. In a preferred embodiment, a layer of thin film material suitable for the formation of thin film resistors is deposited next, followed by a metal layer that will form the bottom plates of metal-dielectric-metal capacitors. Next, the capacitors'"'"' dielectric layer is deposited to a desired thickness to target a particular capacitance value, followed by the deposition of another metal layer that will form the capacitors'"'"' top plates. The metal layers, the capacitor dielectric layer, and the thin film material layer are patterned and etched to form TFRs and metal-dielectric-metal capacitors as desired on the IC substrate. The method may be practiced using any of several alternative process sequences. For example, the bodies of the TFRs can be formed before the deposition of the capacitors'"'"' layers. Also, the capacitors'"'"' bottom plates may be patterned and etched prior to doing the same for their top plates.

Claims

1. A method of fabricating a thin film resistor (TFR) and a capacitor on a common integrated circuit (IC) substrate, comprising:

depositing a first dielectric layer over existing active device and metal interconnect structures on an IC substrate,

depositing a layer of thin film material on said first dielectric layer,

depositing a first layer of metal on said thin film material layer,

depositing a second dielectric layer over said first layer of metal,

depositing a second layer of metal on said second dielectric layer, and

patterning and etching said first and second layers of metal, said second dielectric layer, and said thin film material layer to form a TFR having two endcaps and a metal-dielectric-metal capacitor having top and bottom plates on said IC substrate, said first layer of metal providing said TFR'"'"'s endcaps and said capacitor'"'"'s bottom plate.

2. The method of claim 1, wherein said first dielectric layer comprises plasma-enhanced chemical vapor deposition (PECVD) oxide.

3. The method of claim 1, wherein said thin film material is silicon-chromium-carbon (Si_xCr_yC_z).

4. The method of claim 1, wherein said first metal layer comprises titanium-tungsten (TiW).

5. The method of claim 1, wherein said second dielectric layer comprises plasma-enhanced chemical vapor deposition (PECVD) oxide.

6. The method of claim 1, wherein said second metal layer comprises titanium-tungsten (TiW) and an aluminum-copper alloy.

7. The method of claim 1, wherein said patterning and etching step comprises:

patterning the top plate of said capacitor,

wet etching said second metal layer to define said top plate,

patterning the bottom plate of said capacitor and the body of said TFR,

etching said second dielectric layer, said first layer of metal, and said thin film material to define said bottom plate and the body of said TFR,

patterning an active opening for said TFR, and

etching said second dielectric layer and said first layer of metal from within said patterned opening to define the length of said TFR.

8. A method of fabricating a thin film resistor (TFR) and a capacitor on a common integrated circuit (IC) substrate, comprising:

depositing a first dielectric layer over existing active device and metal interconnect structures on an IC substrate,

depositing a layer of thin film material on said first dielectric layer,

depositing a first layer of metal on said thin film material layer,

depositing a second dielectric layer over said first layer of metal,

depositing a second layer of metal on said second dielectric layer,

patterning and etching said first and second layers of metal, said second dielectric layer, and said thin film material layer to form a TFR and a metal-dielectric-metal capacitor on said IC substrate,

depositing a third dielectric layer over said TFR and capacitor,

etching vias through said third dielectric layer to said TFR and capacitor, and

depositing, patterning and etching a third layer of metal to provide metal interconnections to said TFR and capacitor.

9. A method of fabricating a thin film resistor (TFR) and a metal-oxide-metal capacitor (MOMCAP) on a common integrated circuit (IC) substrate, comprising:

fabricating active devices and a metal interconnect level on an IC substrate,

depositing a first layer of plasma-enhanced chemical vapor deposition (PECVD) oxide over said active devices and said metal interconnect level,

sputter depositing a layer of thin film material on said first PECVD oxide layer,

sputter depositing a first layer of metal on said thin film material layer,

depositing a second layer of PECVD oxide over said first layer of metal,

sputter depositing a second layer of metal on said second PECVD oxide layer,

patterning the top plate of a MOMCAP in said second layer of metal,

wet etching said second metal layer to define said MOMCAP'"'"'s top plate,

patterning the bottom plate of said MOMCAP and the body of a TFR,

etching said second PECVD oxide layer, said first layer of metal, and said thin film material to define said MOMCAP'"'"'s bottom plate and the body of said TFR,

patterning an active opening for said TFR,

etching said second PECVD oxide layer and said first layer of metal from within said patterned opening to define the length of said TFR,

depositing a third PECVD oxide layer over said TFR and capacitor,

etching vias through said third PECVD oxide layer to said TFR and capacitor, and

depositing a third layer of metal on said third PECVD oxide layer and patterning and etching said third layer of metal to provide metal interconnections to said TFR and capacitor.

10. The method of claim 9, wherein said thin film material is silicon-chromium-carbon (Si_xCr_yC_z).

11. The method of claim 9, wherein said first metal layer comprises titanium-tungsten (TiW).

12. The method of claim 9, wherein said second metal layer comprises a titanium-tungsten (TiW) layer and an aluminum-copper (Al—

Cu) alloy layer.

13. The method of claim 12, wherein said TiW layer of said second metal layer has a thickness of between 500-3000 Å

and said Al—

Cu alloy layer has a thickness of between 1000-7000 Å

.

14. The method of claim 9, wherein said first PECVD oxide layer has a thickness of between 1000-6000 Å

.

15. The method of claim 9, wherein said first metal layer has a thickness of between 500-3000 Å

.

16. The method of claim 9, wherein said second PECVD oxide layer has a thickness of between 200-1500 Å

.

17. The method of claim 9, wherein said etching to define said MOMCAP'"'"'s bottom plate and the body of said TFR is accomplished with a single dry etch tool.

18. The method of claim 9, wherein said etching to define said MOMCAP'"'"'s bottom plate and the body of said TFR comprises:

dry etching said bottom plate with a standard CF₄/CHF₃ dry plasma etch,

etching said bottom plate'"'"'s TiW in hot H₂O₂, and

dry etching said thin film material in standard Cl₂ and O₂ chemistry.

19. The method of claim 9, wherein said etching to define said MOMCAP'"'"'s bottom plate and the body of said TFR comprises:

dry etching said bottom plate with a standard CF₄/CHF₃ dry plasma etch,

etching said bottom plate'"'"'s TiW in hot H₂O₂, and

dry etching said thin film material in standard SF₆ chemistry.

20. The method of claim 9, wherein said etching said second PECVD oxide layer and said first layer of metal from within said patterned opening to define the length of said TFR comprises:

dry etching said second PECVD oxide layer with a standard CF₄/CHF₃ dry plasma etch, and

etching said first layer of metal in hot H₂O₂.

21. The method of claim 9, further comprising planarizing said third PECVD oxide using a spin-on glass etch back step.

22. The method of claim 9, further comprising planarizing said third PECVD oxide layer using chemical-mechanical polishing (CMP).

23. A method of fabricating a thin film resistor (TFR) and a metal-dielectric-metal capacitor on a common integrated circuit (IC) substrate, comprising:

fabricating active devices and a metal interconnect level on an IC substrate,

depositing a first dielectric layer over said active devices and said metal interconnect level,

depositing a layer of thin film material on said first dielectric layer,

patterning and etching said thin film layer to define the body of a TFR,

depositing a first layer of metal on said TFR body and said first dielectric layer,

depositing a second dielectric layer over said first layer of metal,

depositing a second layer of metal on said second dielectric layer,

patterning and etching the top plate of a capacitor from said second layer of metal,

patterning and etching the bottom plate of said capacitor and an active opening for said TFR,

depositing a third dielectric layer over said TFR and capacitor,

etching vias through said third dielectric layer to said TFR and capacitor, and

depositing a third layer of metal on said third dielectric layer and patterning and etching said third layer of metal to provide metal interconnections to said TFR and capacitor.

24. The method of claim 23, wherein said second dielectric layer is plasma-enhanced chemical vapor deposition (PECVD) oxide and said etching of said PECVD oxide layer and said first layer of metal to define said bottom plate and said active opening comprises:

performing a standard CF₄/CHF₃ dry plasma etch, and

performing a wet etch in hot H₂O₂.

25. A method of fabricating a thin film resistor (TFR) and a metal-dielectric-metal capacitor on a common integrated grated circuit (IC) substrate, comprising:

fabricating active devices and a metal interconnect level on an IC substrate,

depositing a first dielectric layer over said active devices and said metal interconnect level,

depositing a layer of thin film material on said first dielectric layer,

depositing a first layer of metal on said thin film material layer,

depositing a second dielectric layer over said first layer of metal,

patterning and etching the bottom plate of a capacitor and the body of a TFR from said first layer of metal and said second dielectric layer,

patterning and etching an active opening for said TFR from said first layer of metal and said second dielectric layer,

depositing a second layer of metal on said second dielectric layer,

patterning and etching the top plate of said capacitor from said second layer of metal,

depositing a third dielectric layer over said TFR and capacitor,

etching vias through said third dielectric layer to said TFR and capacitor, and

depositing a third layer of metal on said third dielectric layer and patterning and etching said third layer of metal to provide metal interconnections to said TFR and capacitor.

26. A method of fabricating a thin film resistor (TFR) and a metal-dielectric-metal capacitor on a common integrated circuit (IC) substrate, comprising:

fabricating active devices and a metal interconnect layer on an IC substrate,

depositing a first dielectric layer over said active devices and said metal interconnect level,

depositing a layer of thin film material on said first dielectric level,

patterning and etching said thin film layer to define the body of a TFR,

depositing a first layer of metal on said TFR body and said first dielectric layer,

depositing a second dielectric layer over said first layer of metal,

patterning and etching the bottom plate of a capacitor and an active opening for said TFR from said second dielectric layer and said first metal layer,

depositing a second layer of metal,

patterning and etching the top plate of said capacitor from said second layer of metal,

depositing a third dielectric layer over said TFR and capacitor,

etching vias through said third dielectric layer to said TFR and capacitor, and

depositing a third layer of metal on said third dielectric layer and patterning and etching said third layer of metal to provide metal interconnections to said TFR and capacitor.