Apparatus for manufacturing a semiconductor device and a method for manufacturing a semiconductor device

• US 6,365,492 B1
• Filed: 11/28/2000
• Issued: 04/02/2002
• Est. Priority Date: 01/20/1997
• Status: Expired due to Term

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Okumura, Katsuya, Suguro, Kyoichi
• Primary Examiner(s): Mulpuri, Savitri
• Application Number:
  US09/722,477
• Time in Patent Office: 490 Days
• Field of Search: 438/510, 438/514, 438/530, 438/540, 438/795, 438/946, 250/492.2
• US Class Current: 438/514
• CPC Class Codes: H01J 37/3171 for ion implantation plasma immersion ion implantation H01J37/32412
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/26593 at a temperature lower than room temperature
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence

Abstract

The purpose of the present invention is to avoid a decrease in the mechanical strength of a Si substrate because of the repetition of ion-implantation and annealing processes. As ions are implanted while the Si substrate surface temperature is kept at as low as −60° C. or less. Then the Si substrate is heated to recover the implantation defects caused by the ion-implantation. Such a combination of the low temperature ion-implantation and the annealing processes is repeated as required.

Claims

1. A method for manufacturing a semiconductor device having an ion-implanted source drain diffusion region with a p-n junction comprising:

performing an ion-implantation to a semiconductor substrate arranged within an end station of an ion-implantation apparatus, said end station having a heat sink which is capable of lowering the temperature of surface of the semiconductor substrate;

collecting molecules by using a heat trap which is located in the end station so that the heat trap collects molecules in the end station wherein a valve is connected between the end station and a beam line which an ion-beam passes; and

annealing the semiconductor substrate by a rapid thermal annealing apparatus, the rapid thermal annealing apparatus being capable of heating at a rate of 10°

C./sec or more.

2. The method of manufacturing a semiconductor device having an ion-implanted source drain diffusion region with a p-n junction as claimed in claim 1, wherein said heat sink is capable of cooling under 20°

C.

3. The method for manufacturing a semiconductor device having an ion-implanted source drain diffusion region with a p-n junction as claimed in claim 1, wherein said heat sink is capable of cooling under −

100°

C.

4. The method for manufacturing a semiconductor device having an ion-implanted source drain diffusion region with a p-n junction as claimed in claim 1 further comprising:

making a mask pattern on the semiconductor substrate; and

removing the mask pattern after ion-implanting.

5. The method for manufacturing a semiconductor device having an ion-implanted source drain diffusion region with a p-n junction as claimed in claim 1, wherein the semiconductor substrate is transferred through a wafer carrier chamber having a wafer carrier heat trap for cooling an internal atmosphere of said wafer carrier chamber after a step of performing an ion-implantation.

6. The method for manufacturing a semiconductor device having an ion-implanted source drain diffusion region with a p-n junction as claimed in claim 1, wherein either steps of performing an ion-implantation and annealing are repeated at least two times.

7. A method for manufacturing a semiconductor device as claimed in claim 1, at least one part of a side of said semiconductor substrate being surrounded with a heat trap during said step of implanting.

8. A method for manufacturing a semiconductor device as claimed in claim 1, said heat trap comprising liquid nitrogen.

9. A method for manufacturing a semiconductor device as claimed in claim 1, further comprising a step of preventing said semiconductor substrate from being charged during said step of implanting.

10. A method for manufacturing a semiconductor device as claimed in claim 9, further comprising the step of emitting electrons to said semiconductor substrate.

17. The method of manufacturing a semiconductor device having an ion-implanted source drain diffusion region with a p-n junction as claimed in claim 1, wherein the semiconductor substrate is transferred through a wafer carrier chamber having a wafer carrier heat trap for cooling an internal atmosphere of said wafer carrier chamber after at least a step of performing first or second ion-implantation.

11. A method for manufacturing a semiconductor device having an ion-implanted source drain diffusion region with a p-n junction comprising:

performing a first ion-implantation to a semiconductor substrate arranged within an end station of an ion-implantation apparatus, said end station having a heat sink which is capable of lowering the temperature of surface of the semiconductor substrate;

collecting molecules by using a heat trap which is located in the end station so that the heat trap collects molecules in the end station wherein a valve is connected between the end station and a beam line which an ion-beam passes;

annealing the semiconductor substrate by a rapid thermal annealing apparatus, the rapid thermal annealing apparatus being capable of heating at a rate of 10°

C./ sec or more, after a step of performing the first ion-implantation;

performing a second ion-implantation to the semiconductor substrate arranged within said end station of said ion-implantation apparatus; and

annealing the semiconductor substrate by said rapid thermal annealing apparatus, after a step of performing the second ion-implantation.

12. The method of manufacturing a semiconductor device having an ion-implanted source drain diffusion region with p-n junction as claimed in claim 11,

wherein the semiconductor substrate had a strength of more than 500 MPa at least after the step of performing the second ion-implantation.

13. The method for manufacturing a semiconductor device having at least two ion-implanted diffusion region with a different depth as claimed in claim 11,

wherein said semiconductor substrate with LSI have a strength more than 500 MPa.

14. The method for manufacturing a semiconductor device having an ion-implanted source drain diffusion region with a p-n junction as claimed in claim 11, wherein said heat sink is capable of cooling under 20°

C.

15. The method of manufacturing a semiconductor device having an ion-implanted source drain diffusion region with a p-n junction as claimed in claim 11, wherein said heat sink is capable of cooling under −

100°

C.

16. The method of manufacturing a semiconductor device having an ion-implanted source drain diffusion region with a p-n junction as claimed in claim 11 further comprising:

making a mask pattern on the semiconductor substrate; and

removing the mask pattern after at least a step of performing first or second ion-implantation.