Integrated process for I/O redistribution and passive components fabrication and devices formed

• US 6,365,498 B1
• Filed: 10/15/1999
• Issued: 04/02/2002
• Est. Priority Date: 10/15/1999
• Status: Expired due to Term

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Wen, Ying-Nan, Chu, Tsung-Yao, Lu, Szu-Wei
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Whitmore, Stacy
• Application Number:
  US09/418,651
• Time in Patent Office: 900 Days
• Field of Search: 438/612, 438/614, 438/382, 438/384, 438/381, 438/628
• US Class Current: 438/612
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

The present invention discloses an integrated method for I/O redistribution and in-situ passive components fabrication such that passive components such as resistors and capacitors can be formed simultaneously during the I/O redistribution process. Only minor modifications in the I/O redistribution process need to be made for accomplishing the present invention method. In the method, an adhesion layer formed of a high resistance material such as TiW, TiN, NiCr,or NiV can be used to connect between connective traces and to function as passive resistors. Passive capacitors can be formed by the additional deposition steps of a dielectric layer and a conductive metal layer on top of an existing connective trace formed on a bonding pad.

Claims

1. An integrated process for I/O redistribution and passive components fabrication comprising the steps of:

providing an IC wafer,

depositing an adhesion layer on top of said IC wafer,

depositing a conductive layer on top of said adhesion layer,

coating a first photoresist layer on said conductive layer and patterning to expose areas for forming relocated bonding pads and conductive traces connecting between original bonding pads and relocated bonding pads,

removing said first photoresist layer,

coating a second photoresist layer, and patterning to expose areas of said connective traces,

etching away said conductive layer from areas not covered by said second photoresist layer such that said remaining adhesion layer functions as a resistor between said traces,

removing said second photoresist layer,

depositing and patterning a passivation layer to define the relocated bonding pads.

2. An integrated process for I/O redistribution and passive components fabrication according to claim 1, wherein said adhesion layer is deposited of a material selected from the group consisting of TiW, TiN, Ti, Cr, NiCr, NiV, Ta₂N, W₂N, TaAl, TaTi, TaSi and polysilicon.

3. An integrated process for I/O redistribution and passive components fabrication according to claim 1, wherein said adhesion layer is deposited by a sputtering technique to a thickness between about 100 A and about 5000 A.

4. An integrated process for I/O redistribution and passive components fabrication according to claim 1, wherein said conductive layer is deposited of Cu or Al.

5. An integrated process for I/O redistribution and passive components fabrication according to claim 1, wherein said connective trace is formed of Cu or Al.

6. An integrated process for I/O redistribution and passive components fabrication according to claim 1, wherein said etching process for removing said adhesion layer and said conductive layer is a wet or dry etch process.

7. An integrated process for I/O redistribution and passive components fabrication according to claim 1, wherein said etching process for removing said conductive layer is a dry etch process.

8. An integrated process for I/O redistribution and passive components fabrication according to claim 1 further comprising the step of, after etching away said conductive layer between said connective traces, patterning and etching said adhesion layer such that a passive resistor of a predetermined width and shape is formed.

9. An integrated process for I/O redistribution and passive components fabrication according to claim 1, wherein said predetermined shape is a serpentine shape.

10. An integrated process for I/O redistribution and passive capacitors fabrication comprising the step of:

providing an IC wafer,

depositing an adhesion layer on top of said IC wafer,

depositing a conductive layer on top of said adhesion layer,

coating a photoresist layer on said conductive layer and patterning to form bottom electrodes,

removing said photoresist layer,

conformally depositing and patterning a dielectric layer substantially covering said bottom electrodes,

conformally depositing and patterning a second layer of a conductive metal on top of said dielectric layer insulated from said bottom electrodes, and

the second conductive metal layer acting as top electrodes for the passive capacitors, and defining relocated bonding pads and connective traces.

11. An integrated process for I/O redistribution and passive capacitors fabrication according to claim 10, wherein said adhesion layer is deposited of a material selected from the group consisting of TiW, TiN, Ti, Cr, NiCr, NiV, Ta₂N, W₂N, TaAl, TaTi, TaSi and polysilicon.

12. An integrated process for I/O redistribution and passive capacitors fabrication according to claim 10, wherein said first and second layers of conductive metal are Cu or Al.

13. An integrated process for I/O redistribution and passive capacitors fabrication according to claim 10, wherein said first layer of conductive metal is patterned into a bottom electrode and said second layer of conductive metal is patterned into a top electrode for said passive capacitor.