Method of making a semiconductor device including testing before thinning the semiconductor substrate

• US 6,365,513 B1
• Filed: 09/29/1998
• Issued: 04/02/2002
• Est. Priority Date: 10/01/1997
• Status: Expired due to Term

• Current Assignee: Invensas Corporation
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Tanaka, Tsuyoshi, Ueda, Daisuke, Ishida, Hidetoshi, Furukawa, Hidetoshi, Noma, Atsushi
• Primary Examiner(s): NGUYEN, HA T
• Application Number:
  US09/162,232
• Time in Patent Office: 1,281 Days
• Field of Search: 438/606, 438/459, 438/637-640, 438/666-668, 438/10-12, 438/14, 438/17-18, 438/142, 438/197, 438/233
• US Class Current: 438/667
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A via hole having a bottom is formed in a substrate and then a conductor layer is formed at least over a sidewall of the via hole. Thereafter, the substrate is thinned by removing a portion of the substrate opposite to another portion of the substrate in which the via hole is formed such that the conductor layer is exposed.

Claims

1. A method for fabricating an electronic device, comprising the steps of:

forming a field effect transistor (FET) on a first surface of a substrate;

forming a via hole through the first surface of the substrate;

forming a conductive layer over the first surface of the substrate and a side face of the via hole, the conductive layer including an extended interconnection in a region where the via hole is formed, for testing electrical characteristics of the FET, the extended interconnection being connected with a drain/source region of the FET;

testing electrical characteristics of the FET by using the extended interconnection; and

thinning the substrate by removing a second surface portion of the substrate which is opposite to the first surface such that a portion of the conductive layer formed on the side face of the via hole exposes itself,

wherein the step of testing electrical characteristics of the FET is performed prior to the step of thinning the substrate.

2. A method for fabricating an electronic device, comprising the steps of:

forming a first conductive layer on a first surface of a substrate;

forming an insulator film having a first opening, on the first conductive layer;

forming a resist film having a second opening in an inner portion of the first opening, on the first conductive layer and the insulator film;

forming a hole in the first conductive layer and the substrate using the second opening of the resist film;

depositing a second conductive layer on a wall and bottom of the hole, and on the resist film;

removing a portion of the second conductive layer deposited on the resist film by removing the resist film;

forming a third conductive layer over the first surface of the substrate and an inner portion of the hole, by selectively plating a region of the first conductive layer, which is uncovered by the insulator film and a region of the second conductive layer in the hole, the third conductive layer having an extended interconnection in a first region of the first surface where the hole is formed, for testing electrical characteristics of a device formed in a second region of the first surface; and

thinning the substrate by removing a portion of a second surface of the substrate, which is opposite to the first surface to expose a portion of the third conductive layer formed on the inner portion of the hole.