Method for sorting integrated circuit devices

• US 6,365,860 B1
• Filed: 11/16/2000
• Issued: 04/02/2002
• Est. Priority Date: 01/17/1997
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Beffa, Raymond J.
• Primary Examiner(s): Walsh, Donald P.
• Assistant Examiner(s): Miller, Jonathan R.
• Application Number:
  US09/713,901
• Time in Patent Office: 502 Days
• Field of Search: 209/573, 209/571, 209/572, 324/765, 324/158.1, 324/759
• US Class Current: 209/573
• CPC Class Codes: B07C 5/3412 according to a code applied to the object which indicates a property of the object, e.g. quality class, contents or incorrect indication sorting according to size measured by light-responsive means B07C5/10; sorting according to optical properties B07C5/342; for packages B65D79/02; for information carriers G06K7/00
• CPC Class Codes: B07C 5/344 according to electric or electromagnetic properties sorting according to size measured electrically or electronically B07C5/08; material testing by magnetic means G01N24/00, G01N27/00, by electrical means G01N27/00; electrical measuring devices in general G01R; coin testing G07D5/00
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: H01L 2223/5444 for electrical read out
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An inventive method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, includes automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes. The inventive method can be used in conjunction with an IC manufacturing process that includes providing semiconductor wafers, fabricating the IC'"'"'s on each of the wafers, causing each of the IC'"'"'s to store its ID code, separating each of the IC'"'"'s from its wafer to form IC dice, assembling the IC dice into IC devices, and testing the IC devices. The inventive method is useful for, among other things, culling IC reject bins for shippable IC'"'"'s, sorting IC'"'"'s from a wafer lot into those that require enhanced reliability testing and those that do not, and allowing IC'"'"'s fabricated using both a control fabrication process recipe and a new fabrication process recipe under test to be assembled and tested using the same equipment to reduce unintended test variables introduced when the IC'"'"'s are assembled and tested separately.

Claims

1. An integrated circuit manufacturing process for separating integrated circuit devices for enhanced reliability testing from a group of integrated circuit devices undergoing back-end test procedures, the integrated circuit devices each having a substantially unique identification code, the method comprising:

storing a flag in connection with the identification code of each integrated circuit device of the

integrated circuit devices in the group to indicate whether each integrated circuit device is

in need of enhanced reliability testing;

reading the identification code of each integrated circuit device of the integrated circuit devices

in the group;

accessing the enhanced reliability testing flag stored in connection with each of the read

identification codes;

sorting the integrated circuit devices in the group in accordance with whether their enhanced

reliability testing flag indicates they are in need of enhanced reliability testing; and

performing enhanced reliability testing on integrated circuit devices in the group in need of

enhanced reliability testing.

2. The method of claim 1, wherein the step of sorting the integrated circuit devices in accordance with whether their enhanced reliability testing flag indicates they are in need of enhanced reliability testing comprises sorting the integrated circuit devices in accordance with whether their enhanced reliability testing flag indicates they come from one of a reliable semiconductor wafer and an unreliable semiconductor wafer.