Edge termination of semiconductor devices for high voltages with resistive voltage divider

• US 6,365,930 B1
• Filed: 06/01/2000
• Issued: 04/02/2002
• Est. Priority Date: 06/03/1999
• Status: Expired due to Term

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Ferla, Giuseppe, Schillaci, Antonino, Grimaldi, Antonio
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Ha, Nathan W.
• Application Number:
  US09/585,008
• Time in Patent Office: 670 Days
• Field of Search: 257/339, 257/760, 257/685, 257/773, 257/386, 257/341, 257/346, 357/71, 357/52, 357/53, 357/23, 438/270, 438/271, 438/282
• US Class Current: 257/339
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

Semiconductor device for high voltages including at least one power component and at least one edge termination. The edge termination includes a voltage divider including a plurality of MOS transistors in series, and the edge termination is connected between non-driveble terminals of said power component.

Claims

1. Semiconductor device for high voltages comprising at least one power component and at least one edge termination wherein said edge termination comprises a voltage divider including a plurality of MOS transistors in series, and said edge termination being connected between non-drivable terminals of said power component.

2. Semiconductor device for high voltage according to claim 1, wherein said MOS transistors have active regions formed by silicon stripes of a first conductivity type, said silicon stripes being located inside a silicon layer of a second conductivity type and alternated to portions of said silicon layer, each of said MOS transistors having a gate over said portions of said silicon layer, said gate being formed by one metal layer superimposed on a multi-layer formed by dielectric layers superimposed on a silicon oxide layers, and the channel of each said MOS transistors is parallel to said silicon stripes and is delimited by two polysilicon stripes, said two polysilicon stripes being superimposed on said silicon oxide layers and alternated and underlying said dielectric layers.

3. Semiconductor device for high voltage according to claim 2, wherein said MOS transistors are in diode connection.

4. Semiconductor device for high voltage according to claim 3, wherein said MOS transistors are PMOS transistors and said silicon stripes are P silicon stripes, the source and drain regions of said PMOS transistors being constituted by couples of said stripes contacted by said metal layers.

5. Semiconductor device for high voltage according to claim 1, wherein the body region of said power component and the silicon stripe which is the drain region of a first of said PMOS transistors, are merged together.

6. Semiconductor device for high voltages according to claim 5, wherein said edge terminations are placed in a chip in four sides of a zone wherein said power transistor is located, because each of said edge terminations is located substantially in the middle of each of the four sides.

7. Semiconductor device for high voltages according to claim 6, wherein concentric P silicon rings are provided, which are placed at the periphery of said chip and intersect said edge terminations in order to be intercalated with said P silicon stripes, in order to be adjacent to channels of said PMOS transistors and being connected to P silicon stripes which acts as sources of said PMOS transistors by said metal layers.