Power MOS transistor

• US 6,365,932 B1
• Filed: 07/26/2000
• Issued: 04/02/2002
• Est. Priority Date: 08/20/1999
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Mizuno, Shouji, Kouno, Kenji
• Primary Examiner(s): Ngô , Ngân V.
• Application Number:
  US09/626,479
• Time in Patent Office: 615 Days
• Field of Search: 257/133, 257/146, 257/341, 257/343, 257/370
• US Class Current: 257/341
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/7317 Bipolar thin film transistors
• CPC Class Codes: H01L 29/7394 on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors

Abstract

A new and improved power MOS transistor having a protective diode with an increased breakdown voltage difference and less sheet resistivity is disclosed. In an up-drain type MOSFET, an n-type well layer has its top surface in which an elongated p-type base region is provided adjacent to a deep n⁺-type region (drain region). The p-type base region is formed so that it partly overlaps the deep n⁺ region. A p⁺-type region (p-type base region) is connected to a source electrode. A surge bypassing diode D1 is thus formed between the source and drain of the MOSFET.

Claims

1. A power MOS transistor comprising:

a buried semiconductor layer of a first conductivity type;

a surface side semiconductor layer of the first conductivity type, formed on the buried semiconductor layer, and having an impurity concentration lower than that of the buried semiconductor layer;

a channel region of a second conductivity type, defined in a surface portion of the surface side semiconductor layer;

a source region of the first conductivity type, formed in a surface portion of the channel region;

a gate electrode disposed on at least a part of the channel region in the surface side semiconductor layer with a gate insulation film interposed therebetween;

a deep drain region of the first conductivity type, formed in at least the surface of the surface side semiconductor layer; and

a base region of the second conductivity type, formed in the surface portion of the surface side semiconductor layer to partly overlap with the deep drain region, the base region being connected to a source side to define a surge bypassing diode between the source side and a drain side.

2. A power MOS transistor according to claim 1, wherein:

the power MOS transistor is an up-drain type; and

the drain region is a deep drain region having a depth enough to reach the buried layer from the surface of the surface-side layer.

4. A power MOS transistor according to claim 2, wherein:

the power MOS transistor is an up-drain type; and

the drain region is a deep drain region having a depth enough to reach the buried layer from the surface of the surface-side layer.

5. A power MOS transistor according to claim 2, wherein the power MOS transistor is a lateral drain type.

10. A power MOS transistor according to claim 2, wherein the surge bypassing diode is formed in a separate region other than a transistor formation region.

11. The transistor of claim 1 further comprising:

means for causing a cathode potential of the surge bypassing diode when supplying thereto a maximal current pursuant to surge current application criteria to stay equal to or less than a breakdown voltage at the drain or collector of the transistor.

3. A power MOS transistor comprising:

a buried semiconductor layer of a first conductivity type;

a surface side semiconductor layer of the first conductivity type, formed on the buried semiconductor layer, and having an impurity concentration lower than that of the buried semiconductor layer;

a channel region of a second conductivity type, defined in a surface portion of the surface side semiconductor layer;

a source region of the first conductivity type, formed in a surface portion of the channel region;

a gate electrode disposed on at least a part of the channel region in the surface side semiconductor layer with a gate insulation film interposed therebetween;

a drain region of the first conductivity type, formed in at least the surface of the surface side semiconductor layer; and

a semiconductor region of the first conductivity type, formed in the surface portion of the surface side semiconductor layer, the semiconductor region being connected to a drain side; and

a base region of the second conductivity type, formed in the surface portion of the surface side semiconductor layer to partly overlap with the semiconductor region, the base region being connected to a source side to define a surge bypassing diode between the source side and the drain side.

6. A power MOS transistor comprising:

a semiconductor substrate of a first conductivity type as a drain region;

a surface side semiconductor layer of the first conductivity type, formed on the semiconductor substrate, and having an impurity concentration lower than that of the semiconductor substrate;

a channel region of a second conductivity type, defined in a surface portion of the surface side semiconductor layer;

a source region of the first conductivity type, formed in a surface portion of the channel region;

a gate electrode disposed on at least a part of the channel region in the surface side semiconductor layer with a gate insulation film interposed therebetween;

a deep region of the first conductivity type, formed in at least the surface of the surface side semiconductor layer; and

a base region of the second conductivity type, formed in the surface portion of the surface side semiconductor layer to partly overlap with the deep region, the base region being connected to a source side to define a surge bypassing diode between the source side and a drain side.

7. A power MOS transistor according to claim 6, wherein:

the power MOS transistor is a vertical drain type; and

the deep region having a depth enough to reach the buried layer from the surface of the surface side semiconductor layer.

8. A power MOS transistor comprising:

a buried semiconductor layer of a first conductivity type;

a surface side semiconductor layer of the first conductivity type, formed on the buried semiconductor layer, and having an impurity concentration lower than that of the buried semiconductor layer;

a channel region of a second conductivity type, defined in a surface portion of the surface side semiconductor layer;

an emitter region of the first conductivity type, formed in a surface portion of the channel region;

a gate electrode disposed on at least a part of the channel region in the surface side semiconductor layer with a gate insulation film interposed therebetween;

a collector region of the second conductivity type, formed in at least the surface of the surface side semiconductor layer; and

a semiconductor region of the first conductivity type, formed in the surface portion of the surface side semiconductor layer, the semiconductor region being connected to a collector side; and

a base region of the second conductivity type, formed in the surface portion of the surface side semiconductor layer to partly overlap with the semiconductor region, the base region being connected to an emitter side to define a surge bypassing diode between the source side and the drain side.

9. A power MOS transistor according to claim 8, wherein the power MOS transistor is an integrated gate bipolar transistor.

12. A semiconductor device comprising:

a semiconductor substrate; and

a plurality of active devices formed on the substrate, the active device including a power device and a bipolar transistor plus a double-well CMOS transistor,

wherein the substrate has a semiconductor well region of a first conductivity type and a well region of a second conductivity type, the well regions is for use with the double-well CMOS transistor, the well regions are also formed in both a power device formation region and a bipolar transistor formation region respectively to thereby make up the power device and the bipolar transistor therein.

13. A semiconductor device according to claim 12, wherein the power device is a lateral type MOSFET.

14. A semiconductor device according to claim 12, wherein the power device is an IGBT.

15. A semiconductor device according to claim 12, wherein the power device is a thyristor.