Switching voltage regulator with dual modulation control scheme

• US 6,366,070 B1
• Filed: 07/12/2001
• Issued: 04/02/2002
• Est. Priority Date: 07/12/2001
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Redl, Richard, Cooke, Philip R.
• Primary Examiner(s): Vu, Bao Q.
• Application Number:
  US09/903,942
• Time in Patent Office: 264 Days
• Field of Search: 323/282, 323/284, 323/285, 323/222, 323/290
• US Class Current: 323/284
• CPC Class Codes: H02M 1/0032 Control circuits allowing low power mode operation, e.g. in standby mode
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A switching voltage regulator employs a “dual modulation” scheme to control the regulator'"'"'s switching components. A control circuit indirectly monitors load current. When the load decreases, the control circuit reduces both the duty ratio and the frequency of the control signals which operate the switching transistors, thereby maintaining a high efficiency level over a wider output current range than can be achieved with fixed-frequency control signals. In a preferred embodiment, the regulator employs three operating modes. For heavy loads, the switching components are operated at a constant frequency. For moderate-to-light loads, the dual modulation control scheme is used. For light loads, the regulator enters a “pulse-skipping” mode which can achieve very low operating frequencies to further improve efficiency. The invention may be used with switching regulators using peak current mode, average current mode, or voltage mode control, as well as buck, buck-boost, and boost power stages.

Claims

1. A switching voltage regulator, comprising:

a power stage which includes at least one switch and an inductor, each of said switches responsive to respective control signals, said power stage connected between an input voltage source and an output voltage terminal, and

a control circuit arranged to provide said control signals to said switches to maintain a desired output voltage at said output voltage terminal, said power stage and said control circuit forming a switching voltage regulator, said control circuit comprising;

an amplifier arranged to provide an output CONTROL which varies with the difference between the voltage V_out at said output voltage terminal and said desired output voltage,

a compensation network connected to said CONTROL output and arranged such that CONTROL provides an accurate indication of the absolute value of a load driven by V_out,

a variable frequency oscillator circuit arranged to provide an output signal CLOCK having a frequency f which varies with CONTROL, and

a switch controller arranged to receive CLOCK and a signal which varies with CONTROL and to provide said control signals to said switches, said switch controller arranged to vary the duty ratio and the frequency of said control signals with CONTROL and f.

2. The regulator of claim 1, further comprising a load connected to said output terminal which conducts a current I_load, said at least one switch comprising first and second switches which close in response to first and second ones of said control signals, respectively, said power stage arranged such that said first switch when closed causes the current in said inductor to increase and said second switch when closed causes the current in said inductor to decrease, said switch controller arranged to reduce the duty ratio of said first control signal and reduce the frequency of said first and second control signals as I_load decreases and to increase the duty ratio of said first control signal and increase the frequency of said first and second control signals as I_load increases.

3. The regulator of claim 1, further comprising a load connected to said output terminal which conducts a current I_load, said at least one switch comprising a first switch which closes in response to a respective one of said control signals, said power stage arranged such that said first switch when closed causes the current in said inductor to increase, said switch controller arranged to reduce the duty ratio of said first control signal and the frequency of said control signals as I_load decreases and to increase the duty ratio of said first control signal and the frequency of said control signals as I_load increases.

4. The regulator of claim 3, wherein said switch controller comprises a set-reset flip-flop having its set input connected to CLOCK and its reset input connected to said signal which varies with CONTROL, said control signals derived from s aid flip-flop'"'"'s Q output.

5. The regulator of claim 4, wherein said control circuit is arranged to provide peak current mode control of said regulator, said control circuit further comprising a PWM comparator connected to receive a first input which varies with the current in said inductor and a second input which varies with CONTROL and to produce said signal which varies with CONTROL and is connected to said reset input such that the duty ratio of said first control signal is reduced as I_load decreases and is increased as I_load increases.

6. The regulator of claim 5, wherein said amplifier is a transconductance amplifier.

7. The regulator of claim 4, wherein said control circuit is arranged to provide average current mode control of said regulator, said control circuit further comprising:

a current error amplifier arranged to receive a first input which varies with the current in said inductor and a second input which varies with CONTROL and to produce an output which varies with the average inductor current, and

a PWM comparator connected to receive the output of said current error amplifier at a first input and a sawtooth waveform having a frequency which varies with f at a second input and to produce said signal which varies with CONTROL and is connected to said reset input such that the duty ratio of said first control signal is reduced as I_load decreases and is increased as I_load increases.

8. The regulator of claim 4, wherein said control circuit is arranged to provide voltage mode control of said regulator, said control circuit further comprising a PWM comparator connected to receive a signal which varies with CONTROL at a first input and a sawtooth waveform having a frequency which varies with f at a second input and to produce said signal which varies with CONTROL and is connected to said reset input such that the duty ratio of said first control signal is reduced as I_load decreases and is increased as I_load increases.

9. The regulator of claim 4, wherein said set-reset flip-flop is a reset dominant set-reset flip-flop.

10. The regulator of claim 1, wherein said variable frequency oscillator circuit is arranged to produce said output signal CLOCK with frequency f equal to a first fixed frequency f₁ when CONTROL is greater than a first threshold value and to vary f with CONTROL when CONTROL is below said first threshold value.

11. The regulator of claim 1, wherein said variable frequency oscillator circuit is arranged to produce said output signal CLOCK with frequency f equal to a first fixed frequency f₁ when CONTROL is greater than a first threshold value and with frequency f equal to or less than a second fixed frequency f₂ which is less than f₁ when CONTROL is less than a second threshold value and to vary f with CONTROL when CONTROL is between said first and second threshold values.

12. The regulator of claim 1, further comprising a circuit which detects when the regulator operates in continuous inductor current mode (CCM) during which the current in said inductor remains greater than zero during a switching cycle and detects when the regulator operates in discontinuous inductor current mode (DCM) during which the current in said inductor reaches zero during a switching cycle, said variable frequency oscillator circuit arranged to produce said output signal CLOCK with frequency f equal to a first fixed frequency f₁ when said regulator operates in CCM and to vary f with CONTROL when said regulator operates in DCM.

13. The regulator of claim 1, wherein said output stage is a buck converter power stage.

14. The regulator of claim 1, wherein said output stage is a boost converter power stage.

15. The regulator of claim 1, wherein said output stage is a buck-boost converter power stage.

16. The regulator of claim 1, wherein said at least one switch comprises first and second switches, said control circuit arranged such that said first switch when closed causes the current in said inductor to increase and said second switch when closed causes the current in said inductor to decrease.

17. The regulator of claim 1, wherein said at least one switch comprises one switch, said power stage further comprising a diode, said control circuit and power stage arranged such that said switch when closed causes the current in said inductor to increase and said current in said inductor decreases through said diode when said first switch is off.

18. A switching voltage regulator employing peak current mode control, comprising:

a power stage which includes first and second switches and an inductor, said switches responsive to first and second control signals, respectively, said power stage connected between an input voltage source and an output voltage terminal, and

a control circuit arranged to provide said control signals to said switches to maintain a desired output voltage at said output voltage terminal, said power stage and said control circuit forming a switching voltage regulator, said control circuit comprising;

an amplifier arranged to provide an output CONTROL which varies with the difference between the voltage V_out at said output voltage terminal and said desired output voltage,

a compensation network connected to said CONTROL output and arranged such that CONTROL provides an accurate indication of the absolute value of a load driven by V_out,

a variable frequency oscillator circuit arranged to provide an output signal CLOCK having a frequency f which varies with CONTROL,

a PWM comparator connected to receive a signal which varies with the current in said inductor at a first input and a signal which varies with CONTROL at a second input, and to produce an output signal which toggles when said first input signal increases to match the absolute value of said second input signal, and

a set-reset flip-flop having its set input connected to CLOCK and its reset input connected to said PWM comparator output, said control signals derived from said flip-flop'"'"'s Q output,

said amplifier, PWM comparator and flip-flop arranged such that said CLOCK signal sets said flip-flop, thereby turning on said first switch and turning off said second switch such that the current in said inductor increases, and said PWM comparator output resets said flip-flop, thereby turning off said first switch and turning on said second switch such that the current in said inductor decreases, such that the peak current in said inductor is controlled and the duty ratio and frequency of said control signals vary with CONTROL and f.

19. The regulator of claim 18, further comprising a load connected to said output terminal which conducts a current I_load said power stage arranged such that said first switch when closed causes the current in said inductor to increase and said second switch when closed causes the current in said inductor to decrease, said control circuit arranged to reduce the duty ratio of said first control signal and reduce the frequency of said first and second control signals as I_load decreases and to increase the duty ratio of said first control signal and increase the frequency of said first and second control signals as I_load increases.

20. The regulator of claim 18, wherein said amplifier is voltage amplifier.

21. The regulator of claim 18, wherein said amplifier is a transconductance amplifier.

22. The regulator of claim 18, further comprising a frequency compensation network connected to the output of said amplifier.

23. The regulator of claim 22, wherein said frequency compensation network comprises a first capacitor connected between said amplifier output and a circuit common point, and a resistor and a second capacitor connected in series between said amplifier output and a circuit common point.

24. The regulator of claim 18, wherein said set-reset flip-flop is a reset dominant set-reset flip-flop.

25. The regulator of claim 18, wherein said variable frequency oscillator circuit is arranged to produce said output signal CLOCK with frequency f equal to a first fixed frequency f₁ when CONTROL is greater than a first threshold value and to vary f with CONTROL when CONTROL is below said first threshold value.

26. The regulator of claim 18, wherein said variable frequency oscillator circuit is arranged to produce said output signal CLOCK with frequency f equal to a first fixed frequency f₁ when CONTROL is greater than a first threshold value and with frequency f equal to or less than a second fixed frequency f₂ which is less than f₁ when CONTROL is less than a second threshold value, and to vary f with CONTROL when CONTROL is between said first and second threshold values.

27. The regulator of claim 18, further comprising a circuit which detects when the regulator operates in continuous inductor current mode (CCM) during which the current in said inductor remains greater than zero during a switching cycle and detects when the regulator operates in discontinuous inductor current mode (DCM) during which the current in said inductor reaches zero during a switching cycle, said variable frequency oscillator circuit arranged to produce said output signal CLOCK with frequency f equal to a first fixed frequency f₁ when said regulator operates in CCM and to vary f with CONTROL when said regulator operates in DCM.

28. The regulator of claim 27, further comprising an output capacitor connected to said output terminal, said regulator arranged such that said first switch when closed causes the current in said inductor to increase and said second switch when closed causes the current in said inductor to decrease, said control circuit arranged to turn off said second switch while the regulator operates in DCM to prevent said second switch from discharging said output capacitor.

29. The regulator of claim 18, wherein said output stage is a buck converter power stage.

30. The regulator of claim 18, wherein said output stage is a boost converter power stage.

31. The regulator of claim 18, wherein said output stage is a buck-boost converter power stage.

32. A switching voltage regulator employing peak current mode control, comprising:

a power stage which includes a switch, a diode, and an inductor, said switch responsive to a control signal, said power stage connected between an input voltage source and an output voltage terminal, said power stage arranged such that the current in said inductor increases when said switch is on and decreases via said diode when said switch is off, and

a control circuit arranged to provide said control signal to said switch to maintain a desired output voltage at said output voltage terminal, said power stage and said control circuit forming a switching voltage regulator, said control circuit comprising;

an amplifier arranged to provide an output CONTROL which varies with the difference between the voltage V_out at said output voltage terminal and said desired output voltage,

a compensation network connected to said CONTROL output and arranged such that CONTROL provides an accurate indication of the absolute value of a load driven by V_out,

a variable frequency oscillator circuit arranged to provide an output signal CLOCK having a frequency f which varies with CONTROL,

a PWM comparator connected to receive a signal which varies with the current in said inductor at a first input and a signal which varies with CONTROL at a second input, and to produce an output signal which toggles when said first input signal increases to match the absolute value of said second input signal, and

a set-reset flip-flop having its set input connected to OSC and its reset input connected to said PWM comparator output, said control signal derived from said flip-flop'"'"'s Q output,

said amplifier, PWM comparator and flip-flop arranged such that said CLOCK signal sets said flip-flop, thereby turning on said first switch such that the current in said inductor increases, and said PWM comparator output resets said flip-flop, thereby turning off said first switch such that the current in said inductor decreases, such that the peak current in said inductor is controlled and the duty ratio and frequency of said control signal varies with CONTROL and f.