Nonvolatile/battery-backed key in PLD

• US 6,366,117 B1
• Filed: 11/28/2000
• Issued: 04/02/2002
• Est. Priority Date: 11/28/2000
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Wong, Jennifer, Trimberger, Stephen M., Goetting, F. Erich, Sowards, Jane W., Pang, Raymond C., Rao, Kameswara K., Kondapalli, Venu M., Frake, Scott O.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Chang, Daniel D.
• Application Number:
  US09/724,973
• Time in Patent Office: 490 Days
• Field of Search: 326/38, 326/39, 326/40, 326/46, 380/277, 380/44, 713/165, 713/171, 713/187, 713/189, 713/200
• US Class Current: 326/38
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

It is sometimes desirable to encrypt a design for loading into a PLD so that an attacker may not learn and copy the design as it is being copied into the PLD. According to the invention, the encrypted design is decrypted by a key or keys within the PLD that are preserved when power is removed by either being stored in nonvolatile memory or by being backed up with a battery that switches into operation when the power is removed from the PLD.

Claims

1. A method for configuring a PLD comprising the steps of:

loading a decryption key into the PLD;

placing the decryption key into a state that the decryption key is not erased when external power is removed from the PLD;

storing an encrypted configuration bitstream in a structure different from the PLD;

loading the encrypted configuration bitstream into the PLD;

inside the PLD, decrypting the encrypted configuration bitstream using the decryption key to produce a decrypted bitstream; and

configuring the PLD using the decrypted bitstream.

2. The method of claim 1 wherein the step of placing the decryption key into a state that the decryption key is not erased when external power is removed from the PLD comprises connecting a battery to leads that provide power to memory that stores the key.

3. The method of claim 1 wherein the step of placing the decryption key into a state that the decryption key is not erased when external power is removed from the PLD comprises storing the decryption key in nonvolatile memory in the PLD.

4. A programmable logic device (PLD) comprising:

configurable logic configured by a configuration memory;

structure for receiving a bitstream from a source external to the PLD;

a key memory for storing a decryption key;

a decryptor having a decryption algorithm for decrypting the encrypted configuration bits in the bitstream using the key, and thereby forming configuration data;

structure for loading the configuration data into the configuration memory; and

structure for retaining the key stored in the key memory when power to the remainder of the PLD is removed.

5. The PLD of claim 4 wherein a battery provides backup power to the key memory when power to the remainder of the PLD is removed.

6. The PLD of claim 4 wherein the key memory is nonvolatile.

7. The PLD of claim 4, wherein the bitstream includes unencrypted configuration bits and encrypted configuration bits.