Digital CMOS voltage interface circuits
First Claim
1. A CMOS voltage interface circuit having an input node which provides an input signal to said interface circuit and also an output node, said interface circuit comprising an input signal conditioning block connected to said input node and providing first and second output signals corresponding to said input signal, and an interface block responsive to said first and second output signals which provides at least a different output signal having a selected output level, the signal conditioning block has means which cause said first and second outputs to switch states when the input signal is switching state and which provide said first and second output signals in high state and low state when overlapping, and one of said first and second output signals high and the other of said first and second output signals low, when said first and second output signals are not overlapping, where the interface block has two inputs and two outputs between which are connected two NMOS and two PMOS transistors, where the NMOS transistors are driven by the inputs and the PMOS transistors are driven by the outputs.
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Abstract
CMOS voltage interface circuits have low power consumption, and minimal delays and power dissipation for the driving strength of the output. The circuits use a interface block which is operative upon the applied input signal, depending upon its state and timing, to generate the output at a specified voltage level which may be different from the level of the applied input.
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Citations
30 Claims
- 1. A CMOS voltage interface circuit having an input node which provides an input signal to said interface circuit and also an output node, said interface circuit comprising an input signal conditioning block connected to said input node and providing first and second output signals corresponding to said input signal, and an interface block responsive to said first and second output signals which provides at least a different output signal having a selected output level, the signal conditioning block has means which cause said first and second outputs to switch states when the input signal is switching state and which provide said first and second output signals in high state and low state when overlapping, and one of said first and second output signals high and the other of said first and second output signals low, when said first and second output signals are not overlapping, where the interface block has two inputs and two outputs between which are connected two NMOS and two PMOS transistors, where the NMOS transistors are driven by the inputs and the PMOS transistors are driven by the outputs.
- 2. A CMOS voltage interface circuit having an input node which provides an input signal to said interface circuit and also an output node, said interface circuit comprising an input signal conditioning block connected to said input node and providing first and second output signals corresponding to said input signal, and an interface block responsive to said first and second output signals which provides at least a different output signal having a selected output level, the signal conditioning block has means which provide said first and second signals in non-overlapping relationship during their high state, in overlapping relationship during their low state and when one of said first and second output signals is low the other thereof is high, and where said signal conditioning circuit has means whereby said first and second outputs switch state when said input signal switch state, where the interface block has two inputs and two outputs between which are connected two NMOS and two PMOS transistors, where the NMOS transistors are driven by the inputs and the PMOS transistors are driven by the outputs.
- 7. A CMOS voltage interface circuit having an input node which provides an input signal to said interface circuit and also an output node, said interface circuit comprising an input signal conditioning block connected to said input node and providing first and second output signals corresponding to said input signal, and an interface block responsive to said first and second output signals which provides at least a different output signal having a selected output level, the signal conditioning block has means which cause said first and second outputs to switch states when the input signal is switching state and which provide said first and second output signals in high state and low state when overlapping, and one of said first and second output signals high and the other of said first and second output signals low, when said first and second output signals are not overlapping, wherein the interface block has an NMOS transistor and means including said NMOS transistor for producing the high to low output transition from the interface circuit which NMOS transistor is directly driven from the input of the interface circuit, the interface block including a PMOS transistor and means for producing the low to high output transition from the interface via a feedback loop controlled by both input and output signals of the interface.
- 8. A CMOS voltage interface circuit having an input node which provides an input signal to said interface circuit and also an output node, said interface circuit comprising an input signal conditioning block connected to said input node and providing first and second output signals corresponding to said input signal, and an interface block responsive to said first and second output signals which provides at least a different output signal having a selected output level, the signal conditioning block has means which provide said first and second signals in non-overlapping relationship during their high state, in overlapping relationship during their low state and when one of said first and second output signals is low the other thereof is high, and where said signal conditioning circuit has means whereby said first and second outputs switch state when said input signal switch state, wherein the interface block has an NMOS transistor and means including said NMOS transistor for producing the high to low output transition from the interface circuit which NMOS transistor is directly driven from the input of the interface circuit, the interface block including a PMOS transistor and means for producing the low to high output transition from the interface via a feedback loop controlled by both input and output signals of the interface.
- 13. A CMOS voltage interface circuit having an input node which provides an input signal to said interface circuit and also an output node, said interface circuit comprising an input signal conditioning block connected to said input node and providing first and second output signals corresponding to said input signal, and an interface block responsive to said first and second output signals which provides at least a different output signal having a selected output level, where said first output signal is provided at drains of an NMOS and a PMOS transistor that have gates connected to said input node and said second output signal is provided at the source of said NMOS transistor and the drain of another NMOS transistor.
- 17. A CMOS voltage interface circuit having an input node which provides an input signal to said interface circuit and also an output node, said interface circuit comprising an input signal conditioning block connected to said input node and providing first and second output signals corresponding to said input signal, and an interface block responsive to said first and second output signals which provides at least a different output signal having a selected output level, where said first output signal is provided at drains of an NMOS and a first PMOS transistor that have gates connected to said input node, and said second output signal is provided at the source of said first PMOS transistor and the drain and gate of a second PMOS transistor.
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21. A CMOS voltage interface circuit having an input node which provides an input signal to said CMOS voltage interface circuit, and an output node which provides an output signal from said CMOS voltage interface circuit, said interface circuit comprising:
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(a) circuits operating respectively from two power supplies, providing voltages, VDD-low and VDD-high with VDD-high>
VDD-low, the circuit operating at said VDD-low being connected between a voltage supply rail VDD-low and another voltage supply rail ground, and accepting and generating only logic signals corresponding to nominal values of logic-low=0 volts (or ground potential) and logic-high=VDD-low volts, while the circuit operating at said VDD-high being connected between a voltage supply rail VDD-high and another voltage supply rail ground, and accepting logic signals corresponding to nominal values of logic-low=0 volts (or ground potential) and logic-high=VDD-low volts as well as logic-high=VDD-high volts, and generating only logic signals corresponding to nominal values of logic-low=0 volts (or ground potential) and logic high=VDD-high volts;
(b) said circuits being in a signal conditioning block operating at said VDD-low, and an interface block and a buffer block, both operating at said VDD-high;
(c) said signal conditioning block receiving as input said input signal and generating first and second output signals that switch states only when said input signal switches states, and where the said first and second output signals can be in non-overlapping relationship while in high logic state;
(d) said interface block having two NMOS (first and second) and two PMOS (first and second) transistors, said first and second output signals drive respectively said first and second NMOS transistors, the drains of said first and second NMOS transistors represent the output nodes of the said interface block (respectively third and fourth output nodes providing third and fourth outputs), and said third and fourth output nodes drive respectively said first and second PMOS transistors, the drain of the said first PMOS transistor is connected to the drain of the said second NMOS transistor, and the drain of the said second PMOS transistor is connected to the drain of the said first NMOS transistor, and the sources of the said first and second NMOS transistors are connected to said ground rail and the sources of said first and second PMOS transistors are connected to said VDD-high rail; and
(e) said buffer block has two inputs represented by the said third and fourth outputs, and generates said output signal. - View Dependent Claims (22)
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23. A CMOS voltage interface circuit having an input node which provides an input signal to said CMOS voltage interface circuit, and an output node which provides an output signal from said CMOS voltage interface circuit, said interface circuit comprising:
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(a) circuits operating respectively from two power supplies, VDD-low and VDD-high with VDD-high>
VDD-low, the circuit operating at said VDD-low being connected between a voltage supply rail VDD-low and another voltage supply rail=0 volts (or ground potential), and accepting and generating only logic signals corresponding to nominal values of logic-low=0 volts (or ground potential) and logic-high=VDD-low volts, while the circuits operating at said VDD-high being connected between a voltage supply rail VDD-high and another voltage supply rail ground, and accepting logic signals corresponding to nominal values of logic-low=0 volts (or ground potential) and logic-high=VDD-low volts as well as logic-high=VDD-high volts, and generating only logic signals corresponding to nominal values of logic-low=0 volts (or ground potential) and logic high=VDD-high volts;
(b) circuits providing a signal conditioning block operating at said VDD-low, and an interface block operating at said VDD-high;
(c) said interface block has an NMOS transistor which is directly driven by said input signal;
(d) said interface block has means including said NMOS transistor for producing the high-to-low transition of said output node; and
(e) said interface block has means, including a PMOS transistor, for producing the low-to-high transition of said output node via a feedback loop controlled by both said input signal and said output signal. - View Dependent Claims (24, 25)
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26. A CMOS voltage interface circuit having an input node which provides an input signal to said CMOS voltage interface circuit, and an output node which provides an output signal to said CMOS voltage interface circuit, said interface circuit comprising:
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(a) a plurality of circuit blocks which operate at only one power supply, VDD-high, and are being connected between a voltage supply rail VDD-high and another voltage supply rail ground;
(b) the said input signal is a logic signal of nominal values of logic-low=0 volts (or ground potential) and logic-high=VDD-low volts with VDD-high>
VDD-low;
(c) means which accepts as an input to said interface circuit, said input signal and generates only logic signals corresponding to nominal values of said logic-low and said logic-high;
(d) said input signal drives an NMOS and a PMOS transistor, where the drains of said NMOS and PMOS transistors are connected together and connected to said output node, the source of said NMOS transistor is connected to said ground rail and the source of said PMOS transistor is connected to an internal node;
(e) said NMOS transistor provides the fast high-to-low transition of said output node; and
(f) means are provided to bias said internal node only when the said input node is in high logic state, whereby minimizing the current flowing through the said PMOS transistor. - View Dependent Claims (27, 28)
(a) means are provided so that said internal node to be biased by a voltage divider that is active and provides said required voltage only when said input node is in logic high state, and when the said bias for said internal node is such that said PMOS transistor is off when said voltage divider is active; and
(b) means are provided for a second PMOS transistor to be driven by a combinatorial circuit having as inputs said output node and a set of conditioning signals driving said voltage divider, where said second PMOS transistor provides the fast low-to-high transition of said output node.
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28. The circuit of claim 26 wherein:
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(a) means are provided so that said internal node to be biased by one or more diode connected MOS transistors placed between the said VDD-high rail and said internal node, so that when the said input node is in high logic state, the said required voltage provides a minimal turn-on state for said PMOS transistor;
(b) a diode connected MOS transistor is a transistor that has the source representing one terminal of an equivalent diode, and the drain and the gate are connected together and represent the second terminal of the equivalent diode; and
(c) means are provided for a second PMOS transistor to be driven by a combinatorial circuit having as main input the said output node and the delayed, negated said output node, where said second PMOS transistor provides the fast low-to-high transition of said output node.
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29. A CMOS voltage interface circuit having an input node which provides an input signal to said CMOS voltage interface circuit, and an output node which provides an output signal to said CMOS voltage interface circuit, said interface circuit comprising:
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(a) a plurality of circuit blocks operating at only one power supply, VDD-high, and are being connected between a voltage supply rail VDD-high and another voltage supply rail ground;
(b) the said input signal is a logic signal of nominal values of logic-low=0 volts (or ground material) and logic-high=VDD-low volts, with VDD-high>
VDD-low;
(c) means which accepts as an input to said interface circuit said input signal and generates only logic signals corresponding to nominal values of said logic-low and said logic-high;
(d) said input signal drives an NMOS and a PMOS transistor, where the drains of said NMOS and PMOS transistors are connected together forming an intermediate output node, where the source of said NMOS transistor is connected to a first internal node, and where the source of said PMOS transistor is connected to a second internal node;
(e) means connected to said intermediate output node for providing an (odd+n) stage buffered output, with n greater or equal to zero and where odd is any odd number;
(f) said first internal node is pulled towards the said logic-low potential by a second NMOS transistor driven by the (odd+n) stage buffered output where n=2, said second NMOS transistor having the source connected to the said ground rail;
(g) said second internal node is pulled towards the said VDD-high volts by a second PMOS transistor driven by the odd stage buffered output, said second PMOS transistor having the source connected to said VDD-high rail;
(h) a third NMOS transistor providing the high-to-low transition of said output node is driven by the said first internal node;
(i) a third PMOS transistor providing the low-to-high transition of said output node is driven by a combinatorial circuit having as inputs the said (odd+2) stage buffered output and said intermediate output node;
(j) a fourth NMOS transistor driven by the negated said intermediate output node is provided as a bleeder for said output node; and
(k) a fourth PMOS transistor driven by the said odd stage buffered output is provided as a bleeder for said output node. - View Dependent Claims (30)
(a) the said second internal node is driven by a fifth PMOS transistor which is driven by a chain of even number of inverters (where even is greater or equal to four), said chain having as input the said second internal node; and
(b) said second NMOS transistor is driven now by a combinatorial circuit (in particular an AND gate) having as inputs said (odd+2) stage buffered output and an internal signal representing the output of an even number of inverters of said chain, where said even number is smaller than four.
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Specification