Double pass band amplifier circuit and a radio frequency reception head

• US 6,366,166 B1
• Filed: 08/30/2000
• Issued: 04/02/2002
• Est. Priority Date: 08/31/1999
• Status: Expired due to Term

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Belot, Didier
• Primary Examiner(s): Shingleton, Michael B
• Application Number:
  US09/654,505
• Time in Patent Office: 580 Days
• Field of Search: 330/252, 330/302, 330/305, 330/311
• US Class Current: 330/252
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2203/45386 the AAC comprising one or more coils in the source circuit
• CPC Class Codes: H03F 2203/45554 the IC comprising one or more coils
• CPC Class Codes: H03F 2203/45704 the LC comprising one or more parallel resonance circuits
• CPC Class Codes: H03F 3/191 Tuned amplifiers H03F3/193, H03F3/195 take precedence
• CPC Class Codes: H03F 3/45089 Non-folded cascode stages

Abstract

An amplifier circuit including at least one first input amplifier; at least one second amplifier cascode-assembled with the first amplifier; and at least one reactive impedance circuit, mounted in series with the second amplifier, the reactive impedance circuit being formed by two impedances respectively exhibiting a maximum value for a first and a second frequency, to form a double-band amplifier circuit.

Claims

1. An amplifier circuit including:

at least one first input amplifier;

at least one second amplifier cascode connected with the at least one first amplifier; and

at least one reactive impedance circuit coupled in series with the at least one second amplifier, including two impedances respectively exhibiting a maximum value for a first and a second frequency, to form a double-band amplifier circuit.

2. The amplifier circuit of claim 1, wherein said impedances are associated in series and are sized to each exhibit a maximum value and a high quality factor on one of the two operating frequencies of the circuit.

3. The amplifier circuit of claim 1, wherein each impedance is formed by an inductance in parallel with a capacitor.

4. The amplifier circuit of claim 3, wherein the respective ratios between the inductance and the capacitor of each impedance range between 3,000 and 4,500.

5. The amplifier circuit of claim 3, wherein the inductances and capacitors of the impedances are sized so that the square root of the ratio between the inductance and the capacitance of the first impedance is greater than 10¹⁰ times the value of the inductance of the second impedance, and that the square root of the ratio between the impedance and the capacitance of the second impedance is greater than 0.5*10¹⁰ times the value of the inductance of the first impedance.

6. The amplifier circuit of claim 1, comprising two identical branches in parallel, each formed of a cascode assembly of a first and of a second amplifier, in series with a reactive impedance circuit.

7. The amplifier circuit of claim 6, comprising differential inputs the respective impedances of which are sized to obtain a wide band matching covering the two operating frequency bands of the amplifier.

8. A receiver circuit, comprising:

a radio frequency signal reception head configured to operate on two bands of different frequencies, the reception head comprising;

at least one first amplifier having an input terminal;

at least one second amplifier connected in cascode with the at least one first amplifier; and

at least one reactive impedance circuit coupled in series with the second amplifier, the at least one reactive impedance circuit including a first impedance exhibiting a maximum value for a first frequency and a second impedance exhibiting a maximum value for a second frequency, the first and second impedances forming a double-band amplifier.

9. The circuit of claim 8, wherein each of the first and second impedances is formed by an inductance coupled in parallel with a capacitor.

10. The circuit of claim 9, further comprising a ratio between the inductance and the capacitor of each impedance, the ratio configured to be in the range of 3,000 to 4,500.

11. The circuit of claim 9, further comprising a ratio between the inductance and the capacitor of each impedance, and wherein the inductances and capacitors of the impedances are sized to have the square root of the ratio between the inductance and the capacitance of the first impedance greater than 10¹⁰ times the value of the inductance of the second impedance, and the square root of the ratio between the impedance and the capacitance of the second impedance is greater than 0.5*10¹⁰ times the value of the inductance of the first impedance.

12. The circuit of claim 8, comprising two identical branches in parallel, each formed of a cascode assembly of the first amplifier and the second amplifier in series with the reactive impedance circuit.

13. The circuit of claim 12, wherein the input terminal of the first amplifier of each branch together comprise differential inputs.

14. The circuit of claim 13, wherein the impedances are sized to obtain a frequency band covering the first and second frequencies of the first and second amplifiers.

15. An amplifier circuit, comprising:

first and second parallel branches, each branch comprising;

a first transistor having a control terminal coupled to a reference terminal, a first terminal coupled to a supply voltage, and a second terminal;

a second transistor having a control terminal coupled to an input, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to a current source; and

a reactive impedance circuit coupled in series between the supply voltage and the first terminal of the first transistor, the reactive impedance circuit comprising series coupled first and second capacitors connected in parallel with series coupled first and second inductances.

16. The circuit of claim 15, comprising a node between the reactive impedance circuit and the first transistor of each parallel branch, each node forming an output, and the control terminals of the second transistors comprise differential inputs.

17. The circuit of claim 16, further comprising an inductance coupled between the current source and the second terminal of the second transistor in each parallel branch.

18. The circuit of claim 17, wherein the current source comprises a single current source coupled to the first and second parallel branches.

19. The circuit of claim 18, further comprising a connection formed between the first and second capacitors and the first and, second inductors in each of the first and second parallel branches.