Pipelined analog-to-digital converter

• US 6,366,230 B1
• Filed: 06/07/2000
• Issued: 04/02/2002
• Est. Priority Date: 06/07/2000
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Zhang, Weibiao, Hester, Richard, Richardson, Donald C.
• Primary Examiner(s): JeanPierre, Peguy
• Assistant Examiner(s): JEANGLAUDE, JEAN BRUNER
• Application Number:
  US09/589,406
• Time in Patent Office: 664 Days
• Field of Search: 341/120, 341/118, 341/161, 341/162, 341/155
• US Class Current: 341/162
• CPC Class Codes: H03M 1/167 all stages comprising simultaneous converters H03M1/165 takes precedence
• CPC Class Codes: H03M 1/361 having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
• CPC Class Codes: H03M 1/442 using switched capacitors

Abstract

A pipelined analog-to-digital converter includes a first stage 700 of an analog-to-digital converter having a first resolution. The first stage 700 includes a three capacitor switched capacitor circuit. The analog-to-digital converter further includes one or more subsequent analog-to-digital converter stages 200. The first and subsequent stages 700 and 200 are pipelined together to provide a digital output signal.

Claims

1. An analog-to-digital converter comprising:

a first stage comprising;

at least three comparators, each comparator having inputs coupled to a respective transition voltage node and an analog input signal node;

a decoder coupled to outputs of each of the comparators, the decoder including at least one output that is related to the magnitude of an analog input signal carried at the analog input signal node;

a switched capacitor circuit including a first input coupled to receive the analog input signal and a second input coupled to receive a variable reference voltage the magnitude of which is selected by the at least one decoder output, the switched capacitor circuit also including an output for carrying a residue signal;

a second stage with an input coupled to the switched capacitor circuit output of the first stage, the second stage comprising an sub-analog-to-digital converter configured to quantize the residue signal.

2. The analog-to-digital converter of claim 1 wherein the switched capacitor circuit includes at least three capacitors.

3. The analog-to-digital converter of claim 2 wherein the switched capacitor circuit includes three capacitors.

4. The analog-to-digital converter of claim 3 wherein the three capacitors comprises a first capacitor, a second capacitor and a third capacitor, and wherein:

the first capacitor is coupled between a first reference node and a first input of an amplifier;

the second capacitor is coupled between a second reference node and the first input of the amplifier; and

the third capacitor is coupled between the analog input signal node and the first input of the amplifier.

5. The analog-to-digital converter of claim 4 wherein the capacitance of the second capacitor is about half of the capacitance of the first capacitor.

6. The analog-to-digital converter of claim 4 wherein the first reference node carries a reference voltage equal to one of +1 or −

1 depending on the at least one decoder output and the second reference node carries a reference voltage equal to one of +1 or −

1 depending on the at least one decoder output.

7. The analog-to-digital converter of claim 6 and further comprising:

a first switch with a current path coupled between a +1 reference node and the first reference node, the first switch being controlled by a first decoder output;

a second switch with a current path coupled between a −

1 reference node and the first reference node, the second switch being controlled by a second decoder output;

a third switch with a current path coupled between the +1 reference node and the second reference node, the third switch being controlled by a third decoder output; and

a fourth switch with a current path coupled between the −

1 reference node and the second reference node, the fourth switch being controlled by a fourth decoder output.

8. The analog-to-digital converter of claim 7 wherein each of the first through fourth switches is conductive based on the magnitude of the analog input signal (V_IN) as follows:

when −

1<

V_IN<

−

½

, the first and third switches are non-conductive and the second and fourth switches are conductive;

when −

½

<

V_IN<

0, the first and fourth switches are non-conductive and the second and third switches are conductive;

when 0<

V_IN<

½

, the first and fourth switches are conductive and the second and third switches are non-conductive; and

when ½

<

V_IN<

1, the first and third switches are conductive and the second and fourth switches are non-conductive.

9. The analog-to-digital converter of claim 2 wherein the at least three capacitors comprise first, second, third and fourth capacitors, and wherein the capacitance of the first capacitor is about twice the capacitance of the second capacitor and the capacitance of the second capacitor is about twice the capacitance of the third capacitor.

10. The analog-to-digital converter of claim 9 and further comprising four switches, each of the switches coupled between a respective one of the capacitors and one of a +1 reference node or a −

1 reference node, each switch having a conductivity that is controlled by the at least one decoder output.

11. The analog-to-digital converter of claim 1 wherein the switched capacitor circuit comprises a two capacitor switched capacitor circuit.

12. The analog-to-digital converter of claim 11 wherein the reference voltage that is selected by the at least one decoder output is one of {−

{fraction (3/2)}, −

½

, ½

, {fraction (3/2)}}.

13. The analog-to-digital converter of claim 11 wherein the two capacitors comprise a first capacitor, a second capacitor, and wherein:

the first capacitor is coupled between a reference node and a first input of an amplifier; and

the second capacitor is coupled between the analog input signal and the first input of the amplifier.

14. The analog-to-digital converter of claim 13 wherein the capacitance of the first capacitor is substantially the same as the capacitance of the second capacitor.

15. The analog-to-digital converter of claim 11 wherein a first one of the two capacitors has a capacitance that is about twice that of the second one of the two capacitors.

16. The analog-to-digital converter of claim 15 wherein the reference voltage that is selected by the at least one decoder output is one of {−

¾

, −

¼

, ¼

, ¾

}.

17. The analog-to-digital converter of claim 1 wherein the at least three comparators include a first comparator, a second comparator and a third comparator, and wherein:

the first comparator receives a transition voltage that is substantially equal to about ½

;

the second comparator receives a transition voltage that is substantially equal to about 0; and

the third comparator receives a transition voltage that is substantially equal to about −

½

.

18. A circuit comprising:

a first comparator with a first input coupled to an input signal node and a second input coupled to a first transition voltage node;

a second comparator with a first input coupled to an input signal node and a second input coupled to a second transition voltage node;

a third comparator with a first input coupled to an input signal node and a second input coupled to a third transition voltage node;

a decoder having a first input coupled to an output of the first comparator, a second input coupled to an output of the second comparator and a third input coupled to an output of the third comparator, the decoder further including first, second, third, and fourth outputs;

a first switch with a current path coupled between a +1 reference node and a first plate of a first capacitor, the first switch being controlled by the first decoder output;

a second switch with a current path coupled between a −

1 reference node and the first plate of the first capacitor, the second switch being controlled by the second decoder output;

a third switch with a current path coupled between the +1 reference node and a first plate of a second capacitor, the third switch being controlled by the third decoder output;

a fourth switch with a current path coupled between the −

1 reference node and the first plate of the second capacitor, the fourth switch being controlled by the fourth decoder output;

a fifth switch coupled between the first plate of the first capacitor and the input signal node;

a sixth switch coupled between the input signal node and a first plate of a third capacitor;

an amplifier with a first input coupled to a second plate of the first capacitor, to a second plate of the second capacitor and a second plate of the third capacitor;

a seventh switch coupled between the first plate of the third capacitor and an output of the amplifier;

an eighth switch coupled between the second plate of the third capacitor and the output of the amplifier; and

a ninth switch coupled between the first plate of the second capacitor and a ground reference node.

19. A pipelined analog-to-digital converter comprising:

a first stage of an analog-to-digital converter having a first resolution, the first stage including a three capacitor switched capacitor circuit;

the three capacitor switched capacitor circuit includes a first capacitor, a second capacitor and a third capacitor, and the first capacitor is coupled between a first reference node and a first input of an amplifier, and the second capacitor is coupled between a second reference node and the first input of the amplifier, and the third capacitor is coupled between the analog input signal node and the first input of the amplifier;

one or more subsequent analog-to-digital converter stages, the first and subsequent stages being pipelined together to provide a digital output signal;

a first switch with a current path coupled between a +1 reference node and the first reference node, the first switch being controlled by a first decoder output;

a second switch with a current path coupled between a −

1 reference node and the first reference node, the second switch being controlled by a second decoder output;

a third switch with a current path coupled between the +1 reference node and the second reference node, the third switch being controlled by a third decoder output; and

a fourth switch with a current path coupled between the −

1 reference node and the second reference node, the fourth switch being controlled by a fourth decoder output; and

the first reference node carries a reference voltage equal to one of +1 or −

1 depending on one of said first, second, third or fourth decoder outputs and the second reference node carries a reference voltage equal to one of +1 or −

1 depending on one of said first, second, third or fourth decoder outputs.

20. The analog-to-digital converter of claim 19 wherein each of the first through fourth switches is conductive based on the magnitude of the analog input signal (V_IN) as follows:

when −

1<

V_IN<

−

½

, the first and third switches are non-conductive and the second and fourth switches are conductive;

when −

½

<

V_IN<

0, the first and fourth switches are non-conductive and the second and third switches are conductive;

when 0<

V_IN½

, the first and fourth switches are conductive and the second and third switches are non-conductive; and

when ½

<

V_IN<

1, the first and third switches are conductive and the second and fourth switches are non-conductive.

21. The analog-to-digital converter of claim 19 wherein the capacitance of the second capacitor is about half of the capacitance of the first capacitor.

22. The analog-to-digital converter of claim 19 wherein the first stage has output codes that are not integrally related to output codes of the subsequent stages and all of the output codes contribute to form a digital value.

23. The analog-to-digital converter of claim 19 Wherein the one or more subsequent stages each have a second resolution which is coarser than the first resolution.