Nonvolatile configuration cells and cell arrays

• US 6,366,498 B1
• Filed: 08/30/1999
• Issued: 04/02/2002
• Est. Priority Date: 03/14/1996
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Madurawe, Raminda U., Sansbury, James D.
• Primary Examiner(s): ZARABIAN, AMIR
• Application Number:
  US09/386,082
• Time in Patent Office: 946 Days
• Field of Search: 365/185.23, 365/185.05, 365/185.29, 365/185.18, 365/185.28, 365/185.1
• US Class Current: 365/185.28
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17772 for powering on or off
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H03K 19/17784 for supply voltage

Abstract

A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (515). In one embodiment, the programmable memory element (515) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store the configuration information for a programmable logic device (121).

Claims

1. A method of configuring a programmable memory element comprising:

placing a VEE voltage on a tunnel diode, wherein the tunnel diode is coupled through a tunnel dielectric to a floating gate of the programmable memory element;

placing a first voltage of about VSS or less at a control gate of the programmable memory element;

placing a second voltage of about VSS or less on a drain of the programmable memory element;

passing the second voltage a pull-down device to a source of the programmable memory element; and

transferring electrons from the floating gate through the tunnel dielectric to the tunnel diode, thereby adjusting a threshold voltage of the programmable memory element so that a reasonable voltage on the control gate will turn on the programmable memory element.

2. The method of claim 1 wherein the VEE voltage is a voltage in a range from about 11 volts to about 15 volts.

3. The method of claim 1 wherein the reasonable voltage is a voltage in a range for about VSS to about VDD.

4. The method of claim 1 wherein the reasonable voltage is generated by a charge pump or bias voltage generator.

5. The method of claim 1 wherein the pull-down device is formed using a thin film transistor.

6. The method of claim 1 wherein the pull-down device comprises a transistor.

7. The method of claim 1 wherein the programmable memory element is a Flash or EEPROM cell.

8. The method of claim 1 further comprising:

using an assist voltage to obtain a lower threshold voltage than when the assist voltage is not used.

9. A method of configuring a programmable memory element comprising:

placing a VEE voltage on a tunnel diode, wherein the tunnel diode is coupled through a tunnel dielectric to a floating gate of the programmable memory element;

placing a first voltage of about VSS or less at a control gate of the programmable memory element;

passing a second voltage of about VSS or less through a pull-down resistor to a source node of the programmable memory element; and

transferring electrons from the floating gate through the tunnel dielectric to the tunnel diode to adjust a threshold voltage of the programmable memory element so a voltage from about VSS to about VDD will turn on the programmable memory element.

10. The method of claim 9 wherein the programmable memory element is a Flash of EEPROM cell.

11. The method of claim 9 wherein the VEE voltage is in a range from about 4 volts to about 15 volts.

12. The method of claim 9 wherein the pull-down resistor is formed using a transistor.

13. The method of claim 9 wherein the pull-down resistor is formed using a thin film transistor.

14. The method of claim 9 wherein the pull-down resistor has an impedance from about three megaohms to about one gigaohm.

15. The method of claim 9 further comprising:

placing the second voltage at a drain node of the programmable memory element.

16. The method of claim 15 wherein when a negative second voltage is provided, the threshold voltage of the programmable memory element is adjusted to a lower value than when the second voltage is VSS.

17. The method of claim 9 wherein the tunnel diode is formed using n+ diffusion.

18. The method of claim 9 wherein the electrons are transferred via tunneling.

19. The method of claim 9 wherein the voltage from about VSS to about VDD that will turn on the programmable memory element is applied at a gate of the programmable memory element.

20. The method of claim 9 wherein the voltage from about VSS to about VDD that will turn on the programmable memory element is applied at a control gate of the programmable memory element.

21. The method of claim 9 further comprising:

applying an assist voltage of about VDD or higher to a drain node of the programmable memory element.

22. The method of claim 9 wherein the programmable memory element is an NMOS device, a floating gate device, a Flash transistor, or an EEPROM transistor.

23. The method of claim 9 wherein the second voltage is a negative voltage.