Synchronizing data operations across a synchronization boundary between different clock domains using two-hot encoding
First Claim
1. A circuit comprising:
- a first pointer circuit configured to present a first pointer signal having a 2-hot encoding in response to a first clock signal;
a plurality of registers configured to store data in response to said first pointer signal; and
a selector circuit configured to select said data from said registers in response to a second clock signal.
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Accused Products
Abstract
A digital logic circuit, such as a FIFO memory, includes pointers, or indicators, generated in two clock domains, between which information is transferred, to indicate a location in the digital logic circuit for transferring the information into or out of the digital logic circuit within either clock domain. Each pointer is encoded with a “2-hot” encoded value within one of the clock domains. The 2-hot encoded value of each pointer is sent to the other clock domain to synchronize the pointer to the other clock domain as well as to its original clock domain. Within each clock domain, the pointer generated therein and the pointer received from the other clock domain are used to determine whether the information can be transferred into or out of the digital logic circuit.
104 Citations
20 Claims
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1. A circuit comprising:
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a first pointer circuit configured to present a first pointer signal having a 2-hot encoding in response to a first clock signal;
a plurality of registers configured to store data in response to said first pointer signal; and
a selector circuit configured to select said data from said registers in response to a second clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of synchronizing data between a first clock signal and a second clock signal, the method comprising the steps of:
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(A) generating a write signal having a 2-hot encoding in response to said first clock signal;
(B) storing said data among a plurality of storage units in response to said write signal; and
(C) selecting said data from said storage units in response to said second clock signal. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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20. A circuit comprising:
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means for generating a write signal having a 2-hot encoding in response to a first clock signal;
means for storing data in response to said write signal; and
means for selecting among said data as stored in response to a second clock signal.
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Specification