Network router integrated onto a silicon chip

• US 6,366,583 B2
• Filed: 07/21/1999
• Issued: 04/02/2002
• Est. Priority Date: 08/07/1996
• Status: Expired due to Term

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Collins, Crosswell C., Buell, Eric R., Rowett, Kevin J.
• Primary Examiner(s): NGO, RICKY QUOC
• Application Number:
  US09/359,055
• Publication Number:
  US 20010055323A1
• Time in Patent Office: 986 Days
• Field of Search: 709/250, 709/238, 709/239, 709/212, 370/401, 370/465, 370/466, 370/468, 370/252, 370/400, 370/458, 370/535, 370/536, 370/537, 370/538, 370/539, 370/540, 370/541, 370/542, 370/543, 370/444
• US Class Current: 370/401
• CPC Class Codes: H04L 45/60 Router architectures
• CPC Class Codes: H04L 49/103 using a shared central buffer; using a shared memory
• CPC Class Codes: H04L 49/3018 Input queuing
• CPC Class Codes: H04L 49/3027 Output queuing
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches

Abstract

A router is integrated onto a single silicon chip and includes an internal bus that couples multiple data receive and transmit channels to a central processing unit. The channels each have an external interface for connecting to different LAN or WAN networks. The serial channels are convertible into one or more time division multiplexed (TDM) channels. A time slot assigner (TSA) assembles and disassembles data packets transferred in TDM formats, such as ISDN. The serial channels are used for separately processing data packets in each TDM time slot. The TSA is programmable to operate with different TDM formats. A single direct memory access controller (DMAC) is coupled to each serial channel and an Ethernet channel and conducts data transfers on the internal router bus through a common port. The DMAC uses a novel bus protocol that provides selectable bandwidth allocation for each channel. The router architecture includes different interface circuitry which is also integrated onto the silicon chip. The interface circuitry includes user definable input/output (I/O) pins with programmable pulse width detection. The user definable I/O provides synchronous and asynchronous interfacing to peripheral devices with different timing constraints. The interface circuitry also includes a DRAM controller having a programmable timing control circuit that operates with memory devices having different timing and memory block sizes.

Claims

1. A network processing device, comprising:

multiple channels each coupled to an associated network that transfers data packets having an associated network protocol, the multiple channels each independently transferring the data packets with the associated network;

an internal bus;

a CPU coupled to the internal bus that converts the data packets between each associated network protocol; and

a common DMAC coupled between each one of the multiple channels for routing the data packets between the multiple channels and the internal bus, the DMAC allocating programmable percentages of bandwidth on the internal bus to each of the multiple channels;

the multiple channels, central processing unit, internal bus and DMAC all integrated onto a single silicon chip.

2. A network processing device according to claim 1 including a serial line multiplexer coupled to the multiple channels for receiving and transmitting the data packets in either a serial data stream or a time division multiplexed data stream independently of the CPU.

3. A network processing device according to claim 2 wherein the multiple channels, CPU, internal bus, serial line multiplexer, and DMAC are all integrated onto a single integrated chip.

4. A network processing device, comprising:

multiple channels configured for receiving and transmitting data packets;

a serial line multiplexer coupled to the multiple channels for receiving and transmitting data packets in both a serial data stream and a time division multiplexed data stream; and

a time slot assigner coupled to the serial line multiplexer, the time slot assigner demultiplexing data packets from different time slots in the time division multiplexed data stream into different channels and multiplexing data packets from the multiple channels into a single time division multiplexed data stream;

wherein the time slot assigner includes;

a receive memory for holding receive configuration entries;

receive channel registers associated with each one of the multiple channels; and

a receive selector selectively loading data packets for different time slots in the time division multiplexed data stream into the receive channel registers according to the receive configuration entries in the receive memory.

5. A network processing device according to claim 4 including a current entry counter that addresses a starting location in the receive memory when a synchronization pulse is asserted and increments to a next address in the receive memory for each time slot in the time division multiplexed data stream.

6. A network processing device according to claim 5 including a time slot size counter receiving a time slot period from the receive configuration entries in the receive memory and notifying the current entry counter each time the time slot period expires.

7. A network processing device according to claim 4, wherein the receive configuration entries include:

a count field that identifies an amount of data transferred in the time slot;

a channel select field that identifies which of the channels to transfer the data packets; and

a last field identifying a last entry in the receive memory.

8. A network processing device, comprising:

multiple channels configured for receiving and transmitting data packets;

a serial line multiplexer coupled to the multiple channels for receiving and transmitting data packets in both a serial data stream and a time division multiplexed data stream; and

a time slot assigner coupled to the serial line multiplexer, the time slot assigner demultiplexing data packets from different time slots in the time division multiplexed data stream into different serial channels and multiplexing data packets from the multiple serial channels into a single time division multiplexed data stream;

wherein the time slot assigner circuit includes;

a transmit memory for storing transmit configuration entries;

transmit registers associated with each one of the multiple channels;

a transmit selector selectively outputting the data packets from the transmit registers according to the transmit configuration entries in the transmit memory; and

a transmit multiplexer multiplexing the outputs from the transmit registers into different time slots of the time division multiplexed data stream according to the transmit configuration entries in the transmit memory.

9. A network processing device according to claim 8 including a current entry counter that addresses a starting location in the transmit memory when a synchronization pulse is asserted and increments to a next addressed in the transmit memory for each time slot in the time division multiplexed data stream.

10. A network processing device according to claim 9 including a time slot size counter receiving a time slot period from the transmit configuration entries in the transmit memory and notifying the current entry counter each time the time slot period expires.