Compensation for phase errors caused by clock jitter in a CDMA communication system

• US 6,366,604 B1
• Filed: 12/18/1998
• Issued: 04/02/2002
• Est. Priority Date: 12/18/1998
• Status: Expired due to Term

• Current Assignee: ST-Ericcson SA (Telefonaktiebolaget LM Ericsson)
• Original Assignee: Philips Electronics North America Corporation (Koninklijke Philips N.V.)
• Inventors: Mohindra, Rishi
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): JIANG, LENNY R
• Application Number:
  US09/216,260
• Time in Patent Office: 1,201 Days
• Field of Search: 375/130, 375/135, 375/134, 375/140, 375/141, 375/145, 375/146, 375/150, 375/222, 375/295, 375/296, 375/354, 375/362, 375/371
• US Class Current: 375/146
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04J 13/00 Code division multiplex systems for frequency hopping H04B1/713

Abstract

A CDMA reverse link has a system for providing compensation for phase errors caused by clock jitter in a CDMA reverse link. After filtering, data spread by a pilot PN sequence is supplied to a shift register that produces several data samples for sequential cycles of an internal clock. A memory stores compensation factors representing the clock jitter, pre-calculated for each of the internal clock cycles. A counter counts the internal clock cycles to provide the memory with an address signal indicating a memory location that stores the compensation factor for a current internal clock cycle. Based on the data samples and the compensation factor, an interpolator performs an interpolation algorithm to determine an adjusted spread data value that compensates for phase errors caused by jitter in the internal clock.

Claims

1. A spread spectrum communication system, comprising:

a data spreading circuit for spreading data by a PN sequence and filtering the spread data,

a clock producing circuit for generating an internal clock signal based on a reference clock signal, and

an interpolation circuit for performing interpolation of filtered spread data formed by the data spreading circuit to determine an adjusted spread data value that compensates for a phase error caused by jitter in the internal clock signal.

2. The system of claim 1, wherein said interpolation circuit comprises a shift register controlled by the internal clock signal to produce samples of the filtered spread data for sequential internal clock cycles.

3. The system of claim 2, wherein said interpolation circuit further comprises a memory for storing compensation factors precalculated for each internal clock cycle to compensate for a phase error due to the internal clock jitter.

4. The system of claim 3, wherein said compensation factors represent the internal clock jitter.

5. The system of claim 4, wherein said interpolation circuit further comprises an address generator controlled by the internal clock signal for providing said memory with an address signal indicating a memory location that stores a compensation factor for a current internal clock cycle.

6. The system of claim 5, wherein said interpolation circuit further comprises an interpolator responsive to the samples of the filtered spread data and the compensation factors for calculating the adjusted spread data value.

7. The system of claim 6, wherein said interpolation circuit performs a linear interpolation algorithm to calculate the adjusted spread data value.

8. The system of claim 7, further comprising a digital-to-analog converter responsive to the adjusted spread data value to produce a voltage compensated for the clock jitter.

9. The system of claim 1, wherein said clock producing circuit converts cycles of the reference clock signal into the cycles of the internal clock signal using at least first and second division ratios.

10. The system of claim 9, wherein said clock producing circuit evenly distributes the internal clock cycles produced using the second division ratio over the internal clock cycles produced using the first division ratio.

11. In a CDMA reverse link having a clock generator for producing an internal clock signal based on a reference clock signal, a system for compensating for phase errors caused by jitter in the internal clock signal, comprising:

a sampling circuit responsive to digital data spread by a PN sequence and filtered by a filter for producing spread data samples for sequential internal clock cycles,

a memory for storing compensation factors representing the internal clock jitter, and

an interpolator responsive to the spread data samples and the compensation factors for performing interpolation of filtered spread data to determine adjusted spread data values that compensate for the phase errors caused by the internal clock jitter.

12. The system of claim 11, further comprising a counter controlled by the internal clock signal for providing said memory with an address signal indicating a memory location that stores a compensation factor for a required internal clock cycle.

13. The system of claim 11, wherein said sampling circuit comprises a shift register controlled by the internal clock signal.

14. The system of claim 11, wherein said compensation factors are pre-calculated based on the internal clock jitter and period of the internal clock signal.

15. The system of claim 11, wherein said interpolator performs linear interpolation of the filtered spread data.

16. In a spread spectrum system having an internal clock generator for producing an internal clock signal based on a reference signal, a method of compensating for phase errors caused by jitter in the internal clock signal, comprising the steps of:

sampling digital data spread by a PN sequence and filtered by a filter to produce spread data samples for several sequential internal clock cycles, and

interpolating the spread data samples using compensation factors to determine an adjusted spread data value that compensates for the phase errors caused by the clock jitter.

17. The method of claim 16, wherein a step of sampling comprises the step of shifting the spread digital data controlled by the internal clock signal.

18. The method of claim 16, wherein the compensation factors represent the jitter in the internal clock signal.

19. The method of claim 18, wherein the compensation factors are pre-calculated before the interpolating step.

20. The method of claim 16, wherein said interpolating comprises the step of performing a linear interpolation algorithm.