Video acquisition system including an improved event architecture

• US 6,366,686 B1
• Filed: 01/19/1999
• Issued: 04/02/2002
• Est. Priority Date: 01/19/1999
• Status: Expired due to Term

• Current Assignee: National Instruments Corporation (Emerson Electric Company)
• Original Assignee: National Instruments Corporation (Emerson Electric Company)
• Inventors: Repich, Dan, Schultz, Kevin L., Schroeder, Charles G.
• Primary Examiner(s): Johns, Andrew W.
• Assistant Examiner(s): AZARIAN, SEYED H
• Application Number:
  US09/233,400
• Time in Patent Office: 1,169 Days
• Field of Search: 382/141, 382/140, 382/144, 382/285, 348/312, 348/222, 348/92, 348/143, 348/151, 348/152, 348/153, 348/154, 348/155, 348/156, 340/500, 340/501, 340/540, 340/541
• US Class Current: 382/141
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

A data acquisition (DAQ) system and method which includes an improved event architecture. The DAQ device includes event logic coupled to receive one or more external or internal events from event sources. The event logic comprises one or more event selectors and one or more event mappers. The event selectors and event mappers receive event signals from event sources and selectively route the event signals to one or more destinations, also referred to as destination hardware elements. The destinations are operable to perform an action in response to receipt of the selected event signal. The event architecture of the present invention is designed to take advantage of both the flexibility of the traditional computer interrupt architecture and the speed of direct hardware mapping. At its essence, the hardware architecture comprises a mini, hardware, interrupt service routine. Hardware events or triggers are mapped to a set of board-level Events which are similar to the traditional idea of an interrupt. These hardware Events can then be mapped to cause a wide variety of direct hardware or software actions, similar to the traditional interrupt service routine, with the exception that the hardware events can be made to cause a wide variety of real-time or deterministic responses because no host processing is required.

Claims

1. An image acquisition device for acquiring one or more video images from a video source, the image acquisition device comprising:

an input for receiving video data from a video source;

a buffer memory coupled to said input which stores said digital video data; and

a memory controller coupled to the input and to the buffer memory, wherein the memory controller is operable to write digital video data to the buffer memory and read digital video data from the buffer memory;

event logic coupled to the memory controller and coupled to receive one or more external or internal events, wherein said event logic comprises;

one or more event selectors, wherein each of said event selectors includes a plurality of inputs and at least one output, wherein, for each event selector, at least one of said plurality of inputs is adapted to couple to an event source to receive an event signal from the event source, wherein each of said event selectors is operable to select one of said event signals and provide said selected event signal on said at least one output;

one or more event mappers, wherein each of said one or more event mappers corresponds to at least one of said event selectors, wherein each of said event mappers includes an input which receives one of said selected event signals output from a corresponding one of said event selectors, wherein each of said event mappers is operable to provide said selected event signal to one or more destinations;

wherein said destinations are operable to cause an action to be performed by the image acquisition device in response to receipt of said selected event signal;

a timing/triggering circuit having a plurality of timers and/or counters, each timer and/or counter operable to function independently of the other timers and/or counters;

wherein each one of said one or more event selectors is operable to be assigned to an output of one of the plurality of timers and/or counters, and wherein each one of said one or more event mappers is operable to be assigned to an input of one of the plurality of timers and/or counters, wherein the event logic is operable to generate and sequence separate internal or external events.

2. The image acquisition device of claim 1, wherein said one or more event selectors and said one or more event mappers are configurable to provide an event signal from an event source to a selected destination;

wherein said destinations are operable to cause an action to be performed by the image acquisition device in response to assertion of an event signal by an event source.

3. The image acquisition device of claim 1, further comprising:

one or more destination hardware elements which are each coupled to receive one of said selected event signals output from one of said one or more event mappers, wherein each of said one or more destination hardware elements is operable to perform an action in response to receipt of one of said selected event signals.

4. The image acquisition device of claim 3, wherein said event logic is configurable to enable hardware processing of one or more events by one or more of said destination hardware elements for real time or determinable response requirements.

5. The image acquisition device of claim 3, wherein said one or more destination hardware elements include video capture logic for acquiring video data from the video source.

6. The image acquisition device of claim 3, wherein said one or more destination hardware elements include timing logic for counting a time duration.

7. The image acquisition device of claim 1, wherein the event logic comprises a plurality of event selectors and a plurality of event mappers;

wherein each of said plurality of event mappers corresponds to at least one of said event selectors,

wherein two or more of said event selectors and a corresponding two or more of said event mappers are operable to provide two or more selected event signals to two or more destinations substantially concurrently.

8. The image acquisition device of claim 1, wherein the image acquisition device comprises a board comprised in a computer system;

wherein said event sources are selected from the group comprising;

off-board signals, on-board signals, and software commands.

9. The image acquisition device of claim 1, wherein the image acquisition device comprises a board comprised in a computer system;

the image acquisition device further comprising;

an event interrupt combiner coupled to outputs of one or more of said event mappers, wherein said event interrupt combiner is operable to receive one or more of said selected event signals from said one or more of said event mappers and generate an interrupt signal which is provided to the computer system.

10. The image acquisition device of claim 1, wherein each of said event selectors comprises one or more multiplexers;

wherein each of said event mappers comprises one or more demultiplexers.

11. A data acquisition device for acquiring and/or generating data, the data acquisition device comprising:

a port for receiving and/or generating data;

data acquisition logic for performing data acquisition/generation functions;

a memory coupled to said port which stores received data; and

event logic coupled to the memory controller and coupled to receive one or more external or internal events, wherein said event logic comprises;

one or more event selectors, wherein each of said event selectors includes a plurality of inputs and at least one output, wherein, for each event selector, at least one of said plurality of inputs is adapted to couple to an event source to receive an event signal from the event source, wherein each of said event selectors is operable to select one of said event signals and provide said selected event signal on said at least one output;

one or more event mappers, wherein each of said one or more event mappers corresponds to at least one of said event selectors, wherein each of said event mappers includes an input which receives one of said selected event signals output from a corresponding one of said event selectors, wherein each of said event mappers is operable to provide said selected event signal to one or more destinations;

wherein said destinations are operable to cause an action to be performed by the data acquisition device in response to receipt of said selected event signal;

a timing/triggering circuit having a plurality of timers and/or counters, each timer and/or counter operable to function independently of the other timers and/or counters;

wherein each one of said one or more event selectors is operable to be assigned to an output of one of the plurality of timers and/or counters, and wherein each one of said one or more event mappers is operable to be assigned to an input of one of the plurality of timers and/or counters, wherein the event logic is operable to generate and sequence separate internal or external events.

12. The data acquisition device of claim 11, wherein said one or more event selectors and said one or more event mappers are configurable to provide an event signal from an event source to a selected destination;

wherein said destinations are operable to cause an action to be performed by the data acquisition device in response to assertion of an event signal by an event source.

13. The data acquisition device of claim 11, further comprising:

one or more destination hardware elements which are each coupled to receive one of said selected event signals output from one of said one or more event mappers, wherein each of said one or more destination hardware elements is operable to perform an action in response to receipt of one of said selected event signals.

14. The data acquisition device of claim 13, wherein said event logic is configurable to enable hardware processing of one or more events by one or more of said destination hardware elements for real time or determinable response requirements.

15. The data acquisition device of claim 13, wherein the data acquisition device comprises an add-in board comprised in a computer system.

16. The data acquisition device of claim 11, wherein the data acquisition device comprises a board comprised in a computer system;

wherein said event sources are selected from the group comprising;

off-board signals, on-board signals, and software commands.

17. The data acquisition device of claim 11, wherein the data acquisition device comprises a board comprised in a computer system;

the image acquisition device further comprising;

an event interrupt combiner coupled to outputs of one or more of said event mappers, wherein said event interrupt combiner is operable to receive one or more of said selected event signals from said one or more of said event mappers and generate an interrupt signal which is provided to the computer system.

18. The data acquisition device of claim 11, wherein each of said event selectors comprises one or more multiplexers;

wherein each of said event mappers comprises one or more demultiplexers.

19. A data acquisition device for acquiring and/or generating data, the data acquisition device comprising:

a port for receiving and/or generating data;

data acquisition logic for performing data acquisition/generation functions;

a memory coupled to said port which stores received data;

event logic coupled to the memory controller and coupled to receive one or more external or internal events, wherein the event logic comprises event routing logic, the event routing logic including a plurality of inputs and a plurality of outputs, wherein each of said plurality of inputs is adapted to couple to an event source to receive an event signal, wherein the event routing logic is operable to select at least one of said event signals and output said selected event signal on a selected one of said plurality of outputs to provide said selected event signal to one or more destinations;

wherein said destinations are operable to cause an action to be performed by the data acquisition device in response to receipt of said selected event signal; and

a timing/triggering circuit having a plurality of timers and/or counters, each timer and/or counter operable to function independently of the other timers and/or counters;

wherein each one of said one or more event selectors is operable to be assigned to an output of one of the plurality of timers and/or counters, and wherein each one of said one or more event mappers is operable to be assigned to an input of one of the plurality of timers and/or counters, wherein the event logic is operable to generate and sequence separate internal or external events.

20. The data acquisition device of claim 19, wherein the event routing logic is configurable to provide an event signal from an event source to a selected destination;

wherein said destinations are operable to cause an action to be performed by the data acquisition device in response to assertion of an event signal by an event source.

21. The data acquisition device of claim 19, further comprising:

one or more destination hardware elements which are each coupled to receive one of said selected event signals output from said event routing logic, wherein each of said one or more destination hardware elements is operable to perform an action in response to receipt of one of said selected event signals.

22. The data acquisition device of claim 19, wherein said event logic is configurable to enable hardware processing of one or more events by one or more of said destination hardware elements for real time or determinable response requirements.

23. The data acquisition device of claim 19, wherein the event routing logic comprises:

one or more event selectors, wherein each of said event selectors includes a plurality of inputs and at least one output, wherein, for each event selector, at least one of said plurality of inputs is adapted to couple to an event source to receive an event signal, wherein each of said event selectors is operable to select one of said event signals and provide said selected event signal on said at least one output;

one or more event mappers, wherein each of said one or more event mappers corresponds to at least one of said event selectors, wherein each of said event mappers includes an input which receives one of said selected event signals output from a corresponding one of said event selectors, wherein each of said event mappers is operable to provide said selected event signal to one or more destinations.

24. An image capture system comprising:

a computer system comprising a central processing unit;

an image acquisition device coupled to the computer system for acquiring one or more video images from a video source, the image acquisition device comprising;

an input for receiving video data from a video source;

a buffer memory coupled to said input which stores said digital video data; and

a memory controller coupled to the input and to the buffer memory, wherein the memory controller is operable to write digital video data to the buffer memory and read digital video data from the buffer memory;

event logic coupled to the memory controller and coupled to receive one or more external or internal events, wherein said event logic comprises;

one or more event selectors, wherein each of said event selectors includes a plurality of inputs and at least one output, wherein, for each event selector, at least one of said plurality of inputs is adapted to couple to an event source to receive an event signal from the event source, wherein each of said event selectors is operable to select one of said event signals and provide said selected event signal on said at least one output;

one or more event mappers, wherein each of said one or more event mappers corresponds to at least one of said event selectors, wherein each of said event mappers includes an input which receives one of said selected event signals output from a corresponding one of said event selectors, wherein each of said event mappers is operable to provide said selected event signal to one or more destinations;

wherein said destinations are operable to cause an action to be performed by the image acquisition device in response to receipt of said selected event signal;

wherein said central processing unit on said computer system is not required to service interrupts arising from said event signals.

25. The image capture system of claim 24, wherein the computer system comprises one of:

a personal computer;

a PDA;

an industrial computer;

a PXI computer.

26. The image capture system of claim 24, wherein the image acquisition device further comprises:

a timing/triggering circuit having a plurality of timers and/or counters, each timer and/or counter operable to function independently of the other timers and/or counters;

wherein each one of said one or more event selectors is operable to be assigned to an output of one of the plurality of timers and/or counters, and wherein each one of said one or more event mappers is operable to be assigned to an input of one of the plurality of timers and/or counters, wherein the event logic is operable to generate and sequence separate internal or external events.

27. A data acquisition system comprising:

a computer system comprising a central processing unit;

a data acquisition device coupled to the computer system for acquiring and/or generating data, the data acquisition device comprising;

a port for receiving and/or generating data;

data acquisition logic for performing data acquisition/generation functions;

a memory coupled to said port which stores received data; and

event logic coupled to the memory controller and coupled to receive one or more external or internal events, wherein said event logic comprises;

one or more event selectors, wherein each of said event selectors includes a plurality of inputs and at least one output, wherein, for each event selector, at least one of said plurality of inputs is adapted to couple to an event source to receive an event signal from the event source, wherein each of said event selectors is operable to select one of said event signals and provide said selected event signal on said at least one output;

one or more event mappers, wherein each of said one or more event mappers corresponds to at least one of said event selectors, wherein each of said event mappers includes an input which receives one of said selected event signals output from a corresponding one of said event selectors, wherein each of said event mappers is operable to provide said selected event signal to one or more destinations;

wherein said destinations are operable to cause an action to be performed by the data acquisition device in response to receipt of said selected event signal;

wherein said central processing unit on said computer system is not required to service interrupts arising from said event signals.

28. The data acquisition system of claim 27, wherein the computer system comprises one of:

a personal computer;

a PDA;

an industrial computer;

a PXI computer.

29. The data acquisition system of claim 27, wherein the data acquisition device further comprises:

a timing/triggering circuit having a plurality of timers and/or counters, each timer and/or counter operable to function independently of the other timers and/or counters;

wherein each one of said one or more event selectors is operable to be assigned to an output of one of the plurality of timers and/or counters, and wherein each one of said one or more event mappers is operable to be assigned to an input of one of the plurality of timers and/or counters, wherein the event logic is operable to generate and sequence separate internal or external events.