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Apparatus and method for contact failure inspection in semiconductor devices

  • US 6,366,688 B1
  • Filed: 09/29/1998
  • Issued: 04/02/2002
  • Est. Priority Date: 06/13/1998
  • Status: Expired due to Term
First Claim
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1. A method of inspecting at least a portion of a semiconductor wafer in which at least a portion of a semiconductor integrated circuit is formed, said method comprising:

  • reading scanning electron microscope (SEM) image data for the portion of the semiconductor wafer, the image data for the portion of the semiconductor wafer including pixel data for a plurality of image pixels, the pixel data for each pixel including pixel intensity information for the pixel;

    identifying image data related to a feature of the portion of the integrated circuit in the semiconductor wafer within the data for the portion of the semiconductor wafer;

    computing an image pixel intensity profile for the feature, said computing an image intensity profile for the feature comprising performing a mesh analysis on pixel data for each of a plurality of pixels identified as being related to the feature, the intensity profile comprising a plurality of profile data entries, said performing, a mesh analysis comprising;

    superimposing a coordinate system over an image of the portion of the semiconductor wafer;

    at a plurality of locations along a first axis of the coordinate system, analyzing intensity values of pixels disposed along a second axis of the coordinate system; and

    generating a profile data entry at each of the plurality of locations along the first axis by generating a combination of pixel intensity information for a plurality of the pixels disposed along the second axis;

    computing a parameter related to the feature of the portion of the integrated circuit from the image intensity profile for the feature of the portion of the integrated circuit;

    comparing the parameter to a range of acceptable values for the parameter; and

    using the image pixel intensity profile, classifying the feature of the portion of the integrated circuit according to the comparison with the range of acceptable values for the parameter.

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