Circuit and method of frequency synthesizer control with a serial peripheral interface

• US 6,366,768 B1
• Filed: 11/09/1998
• Issued: 04/02/2002
• Est. Priority Date: 11/09/1998
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Torp, Steven, Tessier, Jesse N. Jr.
• Primary Examiner(s): Nguyen, Duc
• Assistant Examiner(s): Ramakrishnaiah, Melur
• Application Number:
  US09/188,266
• Time in Patent Office: 1,240 Days
• Field of Search: 455/76, 455/260, 455/343, 455/183.1, 455/165.1, 331/16, 331/1.A, 327/105, 327/156, 370/343, 370/344, 375/377
• US Class Current: 455/260
• CPC Class Codes: H04W 52/028 switching on or off only a part of the equipment circuit blocks
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A remote wireless communication device (10) receives messages during windows occurring at predetermined intervals as determined by a communication protocol. The remote wireless communication device uses a microcontroller (28) to initialize the functional blocks (18, 20) and perform message and error processing. The microprocessor and most other functional blocks are disabled between receive message windows to conserve power. A frequency synthesizer control function is incorporated with a serial peripheral interface (38) to the frequency synthesizer to enable the frequency synthesizer just prior and during to the receive message window. The frequency synthesizer control saves power by providing the control necessary to monitor for messages during the window without activating the microcontroller.

Claims

1. An integrated circuit, comprising:

a microcontroller having an output coupled to a bus;

a message control circuit having a first terminal coupled to the bus, a second terminal coupled for receiving data signals, and a third terminal for providing command signals;

a frequency synthesizer control circuit having a first terminal coupled to the bus, a second terminal coupled for receiving the command signals from the message control circuit, and a third terminal for providing a frequency synthesizer control signal even when the microcontroller is not powered; and

a frequency synthesizer that is disabled when the frequency synthesizer control signal has an off state and provides a reference signal when the frequency synthesizer control signal has an on state.

2. The integrated circuit of claim 1 further including a serial peripheral interface circuit having a first terminal coupled to the bus and a second terminal coupled to the first terminal of the message control circuit.

3. The integrated circuit of claim 1 further including:

a receiver having an input coupled for receiving transmitted data and an output coupled to the second terminal of the message control circuit.

4. The integrated circuit of claim 3 wherein the frequency synthesizer control circuit further includes a lock detector circuit coupled to a second output of the frequency synthesizer.

5. An integrated circuit, comprising:

a microcontroller having an output coupled to a bus;

a message control circuit having a first terminal coupled to the bus, a second terminal coupled for receiving data signals, and a third terminal for providing command signals;

a frequency synthesizer control circuit having a first terminal coupled to the bus, a second terminal coupled for receiving the command signals from the message control circuit, and a third terminal for providing a frequency synthesizer control signal; and

a frequency synthesizer that is disabled when the frequency synthesizer control signal has an off state and provides a reference signal when the frequency synthesizer control signal has an on state;

wherein the frequency synthesizer control circuit includes;

a state machine having an input coupled for receiving the command signals from the message control circuit; and

a multiplexer having a first input coupled to the bus, a second input coupled to a first output of the state machine, a control input coupled to a second output of the state machine, and an output coupled to the third terminal of the frequency synthesizer control circuit.

6. The integrated circuit of claim 5 wherein the frequency synthesizer control circuit further includes a serial peripheral interface circuit having a first terminal coupled to the output of the multiplexer and a second terminal coupled to the third terminal of the frequency synthesizer control circuit.

7. The integrated circuit of claim 6 wherein the frequency synthesizer control circuit further includes an I/O interface circuit having a first terminal coupled to the second terminal of the serial peripheral interface circuit and a second terminal coupled to the third terminal of the frequency synthesizer control circuit.

8. The integrated circuit of claim 7 wherein the frequency synthesizer control circuit further includes a bus interface circuit coupled between the bus and the first input of the multiplexer.

9. A wireless communication device, comprising:

a receiver having an input coupled for receiving transmitted data;

a frequency synthesizer having an output for providing a reference frequency to a control input of the receiver;

a microcontroller having an output coupled to a bus;

a message control circuit having a first terminal coupled to the bus, a second terminal coupled for receiving the transmitted data, and a third terminal for providing command signals; and

a frequency synthesizer control circuit having a first terminal coupled to the bus, a second terminal coupled for receiving the command signals from the message control circuit, and a third terminal for providing, even when the microcontroller is not powered, a frequency synthesizer control signal to an input of the frequency synthesizer that disables the frequency synthesizer when in an off state from providing the reference frequency .

10. The wireless communication device of claim 9 further including a serial peripheral interface circuit having a first terminal coupled to the bus and a second terminal coupled to the first terminal of the message control circuit.

11. The wireless communication device of claim 9 wherein the frequency synthesizer control circuit further includes a lock detector circuit coupled to a second output of the frequency synthesizer.

12. A wireless communication device, comprising:

a receiver having an input coupled for receiving transmitted data;

a frequency synthesizer having an output for providing a reference frequency to a control input of the receiver;

a microcontroller having an output coupled to a bus;

a message control circuit having a first terminal coupled to the bus, a second terminal coupled for receiving the transmitted data, and a third terminal for providing command signals; and

a frequency synthesizer control circuit having a first terminal coupled to the bus, a second terminal coupled for receiving the command signals from the message control circuit, and a third terminal for providing a frequency synthesizer control signal to an input of the frequency synthesizer that disables the frequency synthesizer when in an off state from providing the reference frequency;

wherein the frequency synthesizer control circuit includes;

a state machine having an input coupled for receiving the command signals from the message control circuit; and

a multiplexer having a first input coupled to the bus, a second input coupled to a first output of the state machine, a control input coupled to a second output of the state machine, and an output coupled to the third terminal of the frequency synthesizer control circuit.

13. The wireless communication device of claim 12 wherein the frequency synthesizer control circuit further includes a serial peripheral interface circuit having a first terminal coupled to the output of the multiplexer and a second terminal coupled to the third terminal of the frequency synthesizer control circuit.

14. The wireless communication device of claim 13 wherein the frequency synthesizer control circuit further includes an I/O interface circuit having a first terminal coupled to the second terminal of the serial peripheral interface circuit and a second terminal coupled to the third terminal of the frequency synthesizer control circuit.

15. The wireless communication device of claim 14 wherein the frequency synthesizer control circuit further includes a bus interface circuit coupled between the bus and the first input of the multiplexer.