System and a method for defining transforms of memory device addresses

• US 6,366,995 B1
• Filed: 08/19/1999
• Issued: 04/02/2002
• Est. Priority Date: 08/19/1998
• Status: Expired due to Fees

• Current Assignee: Foothills IP LLC
• Original Assignee: Acuid Corp. Ltd.
• Inventors: Deas, Alexander Roger, Vilkov, Boris Nikolaevich
• Primary Examiner(s): Verbrugge, Kevin
• Application Number:
  US09/377,172
• Time in Patent Office: 957 Days
• Field of Search: 711/202, 711/203, 711/206, 714/718
• US Class Current: 711/206
• CPC Class Codes: G11C 29/72 with optimized replacement algorithms
• CPC Class Codes: G11C 29/76 using address translation or modifications

Abstract

A system, a method and a computer program product for defining transforms of cell addresses between different memory device topologies providing the use of minimum memory space and time required for storage and computing defect data and also the flexibility of approach offering a user friendly interface and simplification of the transformation procedure.

Claims

1. A system for defining transforms of memory device addresses between different memory device topologies, each topology having a corresponding address space, the system comprising

a receiving means for receiving a representative plurality of pairs of addresses, each pair consisting of one memory cell address in the first address space and one address in the second address space,

an address pairs storing means for storing said pairs of addresses,

a computing means for computing transformation formulas.

2. A system according to claim 1, wherein the address spaces are selected from the group including logical address space, topological address space, redundancy allocation address space, spatial address space or any other memory device address space.

3. A system according to claim 1, further comprising a transformation map storing means for storing a transformation map as an n×

n matrix of bits and a n×

1 translation vector, where n is the total number of bits in an addresses.

4. A system according to claim 1, further comprising a means for initialization of an address transformation means.

5. A system according to claim 4, wherein the address transformation means are capable of representing mapping as an affine transformation in Pⁿ space, where n denotes the total number of bits in an address, and P is the modulo 2 field.

12. A system according to claim 1, wherein in the receiving means for receiving a representative plurality of pairs of addresses, each pair of addresses consists of one memory cell address Xi, where Xi is a vector combined of n bits of row and column addresses of a memory unit in the first address space, and one address Yi, where Yi is a vector combined of n bits of row and column addresses of a memory unit in the second address space.

13. A system according to claim 12, wherein Xi is a vector combined of n bits of row, column, and DQ addresses of a memory unit in the first address space, and Yi is a vector combined of n bits of row, column, and DQ addresses of a memory unit in the second address space.

14. A system according to claim 1, wherein the address pairs storing means store said pairs of addresses in a matrix form, wherein each address Xi of the pair of addresses is placed in a matrix X, and each address Yi of the pair of addresses is placed in a matrix Y, so that all the addresses Xi, Yi are arranged in the corresponding matrixes X, Y in such a way that a bit containing a value 1 is added to the bottom of each Xi vector, thereby matrix X is (n+1)×

(n+1) matrix, whereas Y is (n+1)×

n matrix.

15. A system according to claim 1, wherein the computing means computes transformation formulas by multiplying matrix Y by inverted matrix X and extracting from the product matrix M which is a (n+1)•

n matrix defined as M=Y×

(X)<sup>−

1</sup> a transformation matrix A as the left n vectors os matrix M, and a translation vector B as the (n+1)^th vector of matrix M, the addresses from one address space into another.

6. A method of defining transforms of memory device addresses between different memory device topologies, each topology having a corresponding address space, the method including:

a step of receiving a representative plurality of pairs of addresses, each pair consisting of one memory cell address in the first address space and one address in the second address space,

a step of storing said pairs,

a step of computing transformation formulas.

7. A method of defining transforms according to claim 6, further comprising a step of transferring the transformation formulas to initialize an affine transformation means.

8. A method according to claim 6, wherein the transformation formulas are transferred to an address transformation means capable of representing mapping as an affine transformation in Pⁿ space, where n denotes the total number of bits in an address, and P is the modulo 2 field.

9. A computer program product comprising a computer usable medium having computer readable program code means embodied in said medium for defining transforms of memory device addresses between different memory device topologies, each topology having a corresponding address space, said computer readable program code means comprising:

a computer readable program code means for causing a computer to receive a representative plurality of pairs of addresses, each pair consisting of one memory cell address in the first address space and one address in the second address space,

a computer readable program code means for causing a computer to store said pairs,

a computer readable program code means for causing a computer to generate transformation formulas,

a computer readable program code means for causing a computer to transfer the transformation formulas to initialize an affine transformation means.

10. A computer program product according to claim 9, further comprising a computer readable program code means for causing a computer to store the transformation map as an n×

n matrix of bits and an n×

1 translation vector, where n is the total number of bits in an address.

11. A computer program product according to claim 9, wherein a computer readable program code means for causing a computer to generate transformation formulas comprises:

a computer readable program code means for causing a computer to sequentially receive said pairs of addresses and place one address from each pair in a matrix X corresponding to the first address space, and the other address in a matrix Y corresponding to the second address space,

a computer readable program code means for causing a computer to calculate a determinant for the matrix X corresponding to the first address space after each pair of addresses is added;

a computer readable program code means for causing a computer to extract some pairs of addresses and/or add some pairs of addresses until a non-zero determinant for the matrix X corresponding to the first address space is obtained;

a computer readable program code means for causing a computer to calculate matrix M as Y·

X<sup>−

1</sup> and extract a transformation matrix and a transformation vector out of the matrix M.