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Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution

  • US 6,366,999 B1
  • Filed: 01/28/1999
  • Issued: 04/02/2002
  • Est. Priority Date: 01/28/1998
  • Status: Expired due to Term
First Claim
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1. A single instruction multiple data stream (SIMD) machine with a controller (SP) and at least two processing elements (PEs), each PE in said SIMD machine comprising:

  • an arithmetic unit which receives at least two operands from a register file;

    instruction control lines derived from a registered instruction that was received from the SP in a processor pipeline, the instruction control lines including conditional execution control lines to control conditional operation as specified in an instruction;

    the arithmetic unit producing a result and a latched arithmetic scalar condition state;

    a first latch for holding the arithmetic scalar condition state for the instruction after the instruction has finished its execution state;

    a second latch connected to the conditional execution control lines for holding instruction control signals for the instruction after the instruction has finished its execution state;

    an arithmetic condition flag (ACF) generation unit for providing a Boolean combination of a present selected state with a previous state; and

    an ACF latch for storing the previous state and feeding the previous state back to the ACF generation unit.

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