System and method for concurrent buffer insertion and placement of logic gates

• US 6,367,051 B1
• Filed: 06/12/1998
• Issued: 04/02/2002
• Est. Priority Date: 06/12/1998
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: Monterey Design Systems, Inc. (Synopsys Incorporated)
• Inventors: Tuncer, Emre, Chakraborty, Abhijeet, Odabasioglu, Altan, Boyle, Douglas B., Malik, Sharad, Pileggi, Lawrence, Pullela, Satyamurthy
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): DO, THUAN V
• Application Number:
  US09/096,810
• Time in Patent Office: 1,390 Days
• Field of Search: 716/12, 716/2, 716/7
• US Class Current: 716/114
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Abstract

A design tool for integrated circuits includes a placement tool which concurrently places logic gates and interconnect. In one embodiment, the logic gates are placed into bins and virtual buffers are inserted between logic gates mapped to different bins. Placement and interconnect wire lengths and densities are successively improved leading to removal of some buffers and actualization of the virtual buffers.

Claims

1. A method for mapping circuit elements of a net list onto a target area of a semiconductor surface, comprising:

partitioning said target area into a plurality of bins;

mapping said circuit elements into said bins;

inserting a buffer between each pair of connected circuit elements placed in bins more than a predetermined distance apart;

optimizing said mapping of said circuit elements in accordance with a cost function, while concurrently inserting and removing buffers when said buffers are mapped into bins based on an insertion criterion and a removal criterion, respectively; and

subdividing said bins into smaller bins, and repeating said optimizing step.

2. A method as in claim 1, wherein said predetermined distance being the distance at which the propagation delay of said buffer substantially equals the delay provided by an interconnect wire of a predetermined width over said distance.

3. A method as in claim 1, wherein each cost estimate of a signal path takes into consideration signal transit time between circuit elements in said signal path.

4. A method as in claim 1, further comprising the step of inserting a buffer when such a buffer both reduces the delay to a far away load and shields the far away load from the nearby load.

5. A method as in claim 1, further comprising the step of inserting a buffer in a critical path when the buffer reduces the delay in said critical path.

6. A method as in claim 1, further comprising inserting a shielding buffer, where a logic gate drives more than a predetermined capacitance related to input terminals of other circuit elements.

7. A method as in claim 1, further comprising dividing said bins in successively smaller bins and repeating said optimizing and removing steps upon said smaller bins.

8. A method as in claim 1, wherein said inserting step places said buffer in a list outside of said net list.

9. A method as in claim 8, wherein said buffer is incorporated into said net list when the distance between said pair of connected circuit elements exceed a predetermined distance.

10. A method as in claim 1, wherein said buffer is removed when said pair of connected circuit elements are separated by less than a predetermined distance.

11. A system for mapping circuit elements of a net list onto a target area of a semiconductor surface, comprising:

a partitioner for partitioning said target area into a plurality of bins each having a predetermined size, and for mapping said circuit elements into said bins;

means for inserting a buffer between each pair of connected circuit elements placed in bins more than a predetermined distance apart; and

a placement tool which optimizes said mapping of said circuit elements in accordance with a cost function, while concurrently inserting and removing buffers when said buffers are mapped into bins based on an insertion criterion and a removal criterion, respectively, wherein said placement tool subdivides said bins into smaller bins as said mapping of said circuit elements is optimized.

12. A system as in claim 11, wherein said predetermined distance being the distance at which the propagation delay of said buffer substantially equals the delay provided by an interconnect wire of a predetermined width over said distance.

13. A system as in claim 11, wherein each cost estimate of a signal path takes into consideration signal transit time between circuit elements in said signal path.

14. A system as in claim 11, said means for inserting a buffer inserts said buffer when such a buffer both reduces the delay to a far away load and shields the far away load from the nearby load.

15. A system as in claim 11, wherein said means for inserting inserts a buffer in a critical path when the buffer reduces the delay in said critical path.

16. A system as in claim 11, said means for inserting further inserts a shielding buffer where a logic gate drives more than a predetermined capacitance related to input terminals of other circuit elements.

17. A system as in claim 11, wherein said partitioner further divides said bins into successively smaller bins and repeatedly invoking said placement tool to place said circuit elements and buffers into said smaller bins.

18. A system as in claim 11, wherein said means for inserting places said buffer in a list outside of said net list.

19. A system as in claim 18, wherein said buffer is incorporated into said net list when the distance between said pair of connected circuit elements exceed a predetermined distance.

20. A system as in claim 11, wherein said buffer is removed when said pair of connected circuit elements are separated by less than a predetermined distance.

21. A system as in claim 11, wherein said circuit elements are interconnected by copper.

22. A system as in claim 11, wherein said circuit elements are interconnected via RF transmission lines carrying high speed mixed mode signals.

23. A system as in claim 11, wherein said target area comprises a micromachine including electronic circuits.