System and method for concurrent buffer insertion and placement of logic gates
First Claim
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1. A method for mapping circuit elements of a net list onto a target area of a semiconductor surface, comprising:
- partitioning said target area into a plurality of bins;
mapping said circuit elements into said bins;
inserting a buffer between each pair of connected circuit elements placed in bins more than a predetermined distance apart;
optimizing said mapping of said circuit elements in accordance with a cost function, while concurrently inserting and removing buffers when said buffers are mapped into bins based on an insertion criterion and a removal criterion, respectively; and
subdividing said bins into smaller bins, and repeating said optimizing step.
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Abstract
A design tool for integrated circuits includes a placement tool which concurrently places logic gates and interconnect. In one embodiment, the logic gates are placed into bins and virtual buffers are inserted between logic gates mapped to different bins. Placement and interconnect wire lengths and densities are successively improved leading to removal of some buffers and actualization of the virtual buffers.
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Citations
23 Claims
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1. A method for mapping circuit elements of a net list onto a target area of a semiconductor surface, comprising:
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partitioning said target area into a plurality of bins;
mapping said circuit elements into said bins;
inserting a buffer between each pair of connected circuit elements placed in bins more than a predetermined distance apart;
optimizing said mapping of said circuit elements in accordance with a cost function, while concurrently inserting and removing buffers when said buffers are mapped into bins based on an insertion criterion and a removal criterion, respectively; and
subdividing said bins into smaller bins, and repeating said optimizing step. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A system for mapping circuit elements of a net list onto a target area of a semiconductor surface, comprising:
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a partitioner for partitioning said target area into a plurality of bins each having a predetermined size, and for mapping said circuit elements into said bins;
means for inserting a buffer between each pair of connected circuit elements placed in bins more than a predetermined distance apart; and
a placement tool which optimizes said mapping of said circuit elements in accordance with a cost function, while concurrently inserting and removing buffers when said buffers are mapped into bins based on an insertion criterion and a removal criterion, respectively, wherein said placement tool subdivides said bins into smaller bins as said mapping of said circuit elements is optimized. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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Specification