Method of fabricating an isolation structure between a vertical transistor and a deep trench capacitor
First Claim
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1. A method of fabricating a horizontal isolation structure between a vertical transistor and a deep trench capacitor, comprising:
- providing a substrate having a pad oxide layer and a silicon nitride layer in turn thereon and a deep trench therein, wherein the deep trench has a deep trench capacitor on the bottom and an upper sidewall portion of the deep trench is exposed;
forming an insulating layer on the substrate and partially filling the deep trench, wherein the thickness of the insulating layer on the sidewall of the deep trench is thinner than that of the insulating layer on the deep trench capacitor and the substrate;
removing the insulating layer on the sidewall of the deep trench to transform the insulating layer into a first insulating layer on the silicon nitride is layer and a second insulating layer on the deep trench capacitor;
forming a protection layer on the second insulating layer;
using wet etching to remove the silicon nitride layer and simultaneously peeling the first insulating layer;
implanting ions into the substrate to form a doped region surrounding the deep trench;
removing the pad oxide layer;
removing the protection layer;
forming a gate oxide layer on the exposed surface of the substrate;
forming a conductive layer on the gate oxide layer and in the deep trench;
forming a shallow trench isolation in the substrate, and the shallow trench isolation partially overlapping the deep trench; and
patterning the conductive layer to form a gate over the deep trench.
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Abstract
A method of fabricating a horizontal isolation structure between a deep trench capacitor and a vertical transistor thereon is provided. A deep trench capacitor is in the bottom of a deep trench of a substrate. An insulating layer is formed to partially fill the deep trench and also on the substrate by high-density plasma chemical vapor deposition. The insulating layer on the sidewall of the deep trench and on the substrate is removed to transform the insulating layer in the deep trench to an isolation structure. An alternative approach is to form an insulating layer on the substrate and in the deep trench. Then a CMP is performed to remove the insulating layer on the substrate and an etching back is performed to remove the upper portion of the insulating layer in the deep trench. Then the remained insulating layer in the deep trench is served as an isolation structure between the deep trench capacitor and a vertical transistor thereron. The upper portion of the insulating layer in the alternative approach is also can be replaced by a low-cost sacrificial layer.
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Citations
19 Claims
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1. A method of fabricating a horizontal isolation structure between a vertical transistor and a deep trench capacitor, comprising:
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providing a substrate having a pad oxide layer and a silicon nitride layer in turn thereon and a deep trench therein, wherein the deep trench has a deep trench capacitor on the bottom and an upper sidewall portion of the deep trench is exposed;
forming an insulating layer on the substrate and partially filling the deep trench, wherein the thickness of the insulating layer on the sidewall of the deep trench is thinner than that of the insulating layer on the deep trench capacitor and the substrate;
removing the insulating layer on the sidewall of the deep trench to transform the insulating layer into a first insulating layer on the silicon nitride is layer and a second insulating layer on the deep trench capacitor;
forming a protection layer on the second insulating layer;
using wet etching to remove the silicon nitride layer and simultaneously peeling the first insulating layer;
implanting ions into the substrate to form a doped region surrounding the deep trench;
removing the pad oxide layer;
removing the protection layer;
forming a gate oxide layer on the exposed surface of the substrate;
forming a conductive layer on the gate oxide layer and in the deep trench;
forming a shallow trench isolation in the substrate, and the shallow trench isolation partially overlapping the deep trench; and
patterning the conductive layer to form a gate over the deep trench. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of fabricating a vertical transistor, comprising:
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providing a substrate sequentially having a pad oxide layer and a silicon nitride layer on the substrate and a deep trench partially filled with a deep trench capacitor, wherein the deep trench has a sidewall;
forming an insulating layer on the substrate and fill the deep trench, wherein the surface of the insulating layer is higher than the surface of the substrate;
removing a portion of the insulating layer until the surface of the silicon nitride layer is exposed and an upper portion of the sidewall is exposed to transform the insulating layer in the deep trench to an isolation layer;
forming a protection layer on the isolation layer;
removing the silicon nitride layer;
implanting ions into the substrate to form a doped region around the deep trench;
removing the pad oxide layer;
removing the protection layer;
forming a gate oxide layer on the exposed surface of the substrate;
forming a conducting layer on the substrate and in the deep trench;
forming a shallow trench isolation in the substrate, and the shallow trench isolation partially overlapping the deep trench; and
patterning the conducting layer to form a gate on the deep trench. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15)
removing the insulating layer above the surface of the silicon nitride layer by chemical mechanical polishing; and
removing an upper portion of the remained insulating layer in the deep trench by dry etching.
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15. The method as claimed in claim 7, wherein the thickness of the isolation layer in the deep trench is about 300 to about 900 Å
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16. A method of fabricating an isolation structure between a deep trench capacitor and a vertical transistor, comprising:
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providing a substrate sequentially having a pad oxide layer and a silicon nitride layer thereon and a deep trench partially filled with a deep trench capacitor;
forming an insulating layer on the substrate and filling the deep trench by high-density plasma chemical vapor deposition, wherein the surface of the insulating layer in the deep trench is about the same level as the surface of the silicon nitride layer;
forming a sacrificial layer on the insulating layer and the surface of the insulating layer is higher than the surface of the substrate by at least about 8000 to about 10000 Å
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removing the sacrificial layer and the insulating layer above the silicon nitride layer by chemical mechanical polishing;
etching back the upper portion of the insulating layer in the deep trench;
and forming a vertical transistor in the deep trench. - View Dependent Claims (17, 18, 19)
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Specification
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Current AssigneeNanya Technology Corporation
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Original AssigneeNanya Technology Corporation
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InventorsLee, Pei-Ing, He, Tzu-En, Chang, Chi-Han, Tsai, Hsin-Chuan
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Primary Examiner(s)Elms, Richard
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Assistant Examiner(s)Pyonin, Adam
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Application NumberUS09/733,888Time in Patent Office487 DaysField of Search438/392, 438/386, 438/391, 438/242, 438/243, 438/248, 438/270, 438/294US Class Current438/248CPC Class CodesH10B 12/0383 wherein the transistor is v...H10B 12/053 the transistor being at lea...
