Manufacture of trench-gate semiconductor devices
First Claim
1. A method of manufacturing a trench-gate semiconductor device having source and drain regions of a first conductivity type which are separated by a channel-accommodating body region adjacent to the trench-gate, including the steps of:
- (a) forming at a surface of a semiconductor body a mask having a window at an area of the body region, (b) introducing dopant of the first conductivity type for the source region into the said area via the window as defined by a masking edge of the window, (c) diffusing the dopant of the first conductivity type into the body region so as to form a surface region of the first conductivity type that extends laterally below the mask at a distance beyond the masking edge of the window, (d) etching a trench into the body at the window to extend through the surface region and body region to an underlying portion of the drain region, the lateral extent of the trench being determined by the etching of the body at tile masking edge of the window to leave the source region adjacent to the trench, (e) depositing material in the trench to provide the gate adjacent to where the channel is accommodated in the body region, and (f) providing a source electrode on the body after removing the mask so as to expose the source region and an adjacent surface portion of the body region for contacting by the source electrode, wherein no intervening step occurs between the introducing step and the diffusing step.
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Accused Products
Abstract
A trench-gate semiconductor device, for example a MOSFET or IGBT, of compact geometry is manufactured with self-aligned masking techniques in a simple process with good reproducibility. The source region (13) of the device is formed by introducing dopant (63) into an area of the body region (15) via a mask window (51a), diffusing the dopant to form a surface region (13b) that extends laterally below the mask (51) at a distance (d) beyond the masking edge (51b) of the window (51a), and then etching the body (10) at the window (51a) to form a trench (20) for the trench-gate (11) with a lateral extent (y) that is determined by the etching of the body (10) at the masking edge (51b) of the window (51a). A portion of the surface region (13b) is left to provide the source region (13) adjacent to the trench (20). The invention permits the etch edge definition for the trench (2) to be better controlled by using the masking edge (51b) of a well-defined mask (51), as compared with the less well defined edges that tend to result from the use of a side-wall extension in prior-art processes.
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Citations
10 Claims
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1. A method of manufacturing a trench-gate semiconductor device having source and drain regions of a first conductivity type which are separated by a channel-accommodating body region adjacent to the trench-gate, including the steps of:
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(a) forming at a surface of a semiconductor body a mask having a window at an area of the body region, (b) introducing dopant of the first conductivity type for the source region into the said area via the window as defined by a masking edge of the window, (c) diffusing the dopant of the first conductivity type into the body region so as to form a surface region of the first conductivity type that extends laterally below the mask at a distance beyond the masking edge of the window, (d) etching a trench into the body at the window to extend through the surface region and body region to an underlying portion of the drain region, the lateral extent of the trench being determined by the etching of the body at tile masking edge of the window to leave the source region adjacent to the trench, (e) depositing material in the trench to provide the gate adjacent to where the channel is accommodated in the body region, and (f) providing a source electrode on the body after removing the mask so as to expose the source region and an adjacent surface portion of the body region for contacting by the source electrode, wherein no intervening step occurs between the introducing step and the diffusing step. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification