Manufacture of trench-gate semiconductor devices

• US 6,368,921 B1
• Filed: 09/28/2000
• Issued: 04/09/2002
• Est. Priority Date: 09/28/1999
• Status: Expired due to Term

• Current Assignee: Nexperia B.V. (Wingtech Technology Co., Ltd.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Timmering, Cornelius E., Hijzen, Erwin A., Maas, Henricus G. R.
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Pyonin, Adam
• Application Number:
  US09/671,888
• Time in Patent Office: 558 Days
• Field of Search: 438/530, 438/555, 438/287, 438/242, 438/259, 438/270, 438/700
• US Class Current: 438/270
• CPC Class Codes: H01L 29/66348 with a recessed gate

Abstract

A trench-gate semiconductor device, for example a MOSFET or IGBT, of compact geometry is manufactured with self-aligned masking techniques in a simple process with good reproducibility. The source region (13) of the device is formed by introducing dopant (63) into an area of the body region (15) via a mask window (51a), diffusing the dopant to form a surface region (13b) that extends laterally below the mask (51) at a distance (d) beyond the masking edge (51b) of the window (51a), and then etching the body (10) at the window (51a) to form a trench (20) for the trench-gate (11) with a lateral extent (y) that is determined by the etching of the body (10) at the masking edge (51b) of the window (51a). A portion of the surface region (13b) is left to provide the source region (13) adjacent to the trench (20). The invention permits the etch edge definition for the trench (2) to be better controlled by using the masking edge (51b) of a well-defined mask (51), as compared with the less well defined edges that tend to result from the use of a side-wall extension in prior-art processes.

Claims

1. A method of manufacturing a trench-gate semiconductor device having source and drain regions of a first conductivity type which are separated by a channel-accommodating body region adjacent to the trench-gate, including the steps of:

(a) forming at a surface of a semiconductor body a mask having a window at an area of the body region,

(b) introducing dopant of the first conductivity type for the source region into the said area via the window as defined by a masking edge of the window,

(c) diffusing the dopant of the first conductivity type into the body region so as to form a surface region of the first conductivity type that extends laterally below the mask at a distance beyond the masking edge of the window,

(d) etching a trench into the body at the window to extend through the surface region and body region to an underlying portion of the drain region, the lateral extent of the trench being determined by the etching of the body at tile masking edge of the window to leave the source region adjacent to the trench,

(e) depositing material in the trench to provide the gate adjacent to where the channel is accommodated in the body region, and

(f) providing a source electrode on the body after removing the mask so as to expose the source region and an adjacent surface portion of the body region for contacting by the source electrode, wherein no intervening step occurs between the introducing step and the diffusing step.

2. A method as claimed in claim 1, wherein an insulating overlayer is formed over the gate before step (f), and the source electrode provided in step (f) extends on the surface of the body and also on the insulating overlayer.

3. A method as claimed in claim 2, wherein the insulating overlayer is formed by deposition of insulating material in the window of the mask, and the mask is selectively etchable with respect to the insulating material of the overlayer thereby permitting removal of the mask while leaving the overlayer over the gate in the trench.

4. A method as claimed in claim 2, wherein the insulating material of the overlayer is selectively etchable with respect to the mask thereby permitting removal of the insulating overlayer from over the mask while leaving the insulating material of the overlayer in the window of the mask.

5. A method as claimed in claim 1, wherein silicon material is deposited on an insulating layer in the trench to form the gate in step (e).

6. A method as claimed in claim 1, wherein silicon material is deposited on an insulating layer in the trench to form the gate in step (e), an upper portion of the silicon material is oxidised to form an insulating overlayer over the gate before step (f), and the source electrode provided in step (f) extends on the surface of the body and also on the insulating overlayer.

7. A method as claimed in claim 1 wherein the mask comprises silicon nitride on a thinner layer of silicon dioxide.

8. A method as claimed in any claim 1 wherein the channel-accommodating body region is a region is of an opposite, second conductivity type.

9. A method as claimed in claim 8, wherein said adjacent surface of the body region that is contacted by the source electrode in step (f) is more highly doped than the channel-accommodating portion of the body region and is formed by introducing dopant of the second conductivity type into the body after removing the mask and before providing the source electrode.

10. A trench-gate semiconductor device manufactured by a method as claimed in claim 1.