Diffusion inhibited dielectric structure for diffusion enhanced conductor layer

• US 6,368,952 B1
• Filed: 08/15/2000
• Issued: 04/09/2002
• Est. Priority Date: 08/15/2000
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Jang, Syun-Ming, Liang, Mong-Song
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): PHAM, THANHHA S
• Application Number:
  US09/638,775
• Time in Patent Office: 602 Days
• Field of Search: 438/453, 438/622, 438/637, 438/638, 438/639, 438/640, 438/672, 438/674, 438/675, 438/687, 438/688, 438/207, 438/218, 438/219, 438/197, 438/199, 438/206, 257/773, 257/774, 257/776, 257/747, 257/374, 257/499, 257/508, 257/509
• US Class Current: 438/622
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Within a method for forming a microelectronic fabrication, there is first provided a substrate. There is then formed over the substrate a microelectronic device passivated with a patterned first dielectric layer in turn annularly surrounded by a patterned second dielectric layer. There is also formed over the substrate a patterned conductor layer separated from the microelectronic device by the patterned first dielectric layer and the patterned second dielectric layer. Within the method: (1) the patterned first dielectric layer is formed from a first dielectric material having a first diffusion coefficient with respect to a conductor material from which is formed the patterned conductor layer; (2) the patterned second dielectric layer is formed from a second dielectric material having a second diffusion coefficient with respect to the conductor material from which is formed the patterned conductor layer; and (3) the first diffusion coefficient is greater than the second diffusion coefficient.

Claims

1. A method for forming a microelectronic fabrication comprising:

providing a substrate;

forming over the substrate a microelectronic device passivated with a patterned first dielectric layer in turn annularly surrounded by a patterned second dielectric layer; and

forming over the substrate a patterned conductor layer separated from the microelectronic device by the patterned first dielectric layer and the patterned second dielectric layer, wherein;

the patterned first dielectric layer is formed from a first dielectric material having a first diffusion coefficient with respect to a conductor material from which is formed the patterned conductor layer;

the patterned second dielectric layer is formed from a second dielectric material having a second diffusion coefficient with respect to the conductor material from which is formed the patterned conductor layer; and

the first diffusion coefficient is greater than the second diffusion coefficient.

2. The method of claim 1 wherein the substrate is employed within a microelectronic fabrication selected from the group consisting of integrated circuit microelectronic fabrications, ceramic substrate microelectronic fabrications, solar cell optoelectronic microelectronic fabrications, sensor image array optoelectronic microelectronic fabrications and display image array optoelectronic microelectronic fabrications.

3. The method of claim 1 wherein the microelectronic device is selected from the group consisting of resistors, transistors, diodes and capacitors.

4. The method of claim 1 wherein the patterned conductor layer is formed at least in part of a copper containing conductor material.

5. The method of claim 1 wherein the patterned first dielectric layer is formed of a dielectric material selected from the group consisting of silicon oxide dielectric material, spin-on-glass (SOG) dielectric materials and spin-on-polymer (SOP) dielectric materials.

6. The method of claim 1 wherein the patterned second dielectric layer is formed a dielectric material selected from the group consisting of silicon nitride dielectric material, silicon carbide dielectric materials, aluminum oxide dielectric material and titanium oxide dielectric materials.

7. The method of claim 1 further comprising over the substrate a third dielectric layer which covers the patterned second dielectric layer and in conjunction with the patterned second dielectric layer encapsulates the microelectronic device with respect to the patterned conductor layer, the third dielectric layer being formed from a third dielectric material having a third diffusion coefficient with respect to the conductor material from which is formed the patterned conductor layer, the third diffusion coefficient being less than the first diffusion coefficient.

8. The method of claim 1 further comprising forming over the substrate a second microelectronic device not annularly surrounded by the patterned second dielectric layer.

9. The method of claim 8 wherein the microelectronic device is employed within a memory circuit formed over the substrate and the second microelectronic device is employed within a logic circuit formed over the substrate.

10. A microelectronic fabrication comprising:

a substrate;

a microelectronic device formed over the substrate and passivated with a patterned first dielectric layer in turn annularly surrounded by a patterned second dielectric layer; and

a patterned conductor layer formed over the substrate and separated from the microelectronic device by the patterned first dielectric layer and the patterned second dielectric layer, wherein;

the patterned first dielectric layer is formed from a first dielectric material having a first diffusion coefficient with respect to a conductor material from which is formed the patterned conductor layer;

the patterned second dielectric layer is formed from a second dielectric material having a second diffusion coefficient with respect to the conductor material from which is formed the patterned conductor layer; and

the first diffusion coefficient is greater than the second diffusion coefficient.

11. The microelectronic fabrication of claim 10 wherein the substrate is employed within a microelectronic fabrication selected from the group consisting of integrated circuit microelectronic fabrications, ceramic substrate microelectronic fabrications, solar cell optoelectronic microelectronic fabrications, sensor image array optoelectronic microelectronic fabrications and display image array optoelectronic microelectronic fabrications.

12. The microelectronic fabrication of claim 10 wherein the microelectronic device is selected from the group consisting of resistors, transistors, diodes and capacitors.

13. The microelectronic fabrication of claim 10 wherein the patterned conductor layer is formed at least in part of a copper containing conductor material.

14. The microelectronic fabrication of claim 10 wherein the patterned first dielectric layer is formed of a dielectric material selected from the group consisting of silicon oxide dielectric material, spin-on-glass (SOG) dielectric materials and spin-on-polymer (SOP) dielectric materials.

15. The microelectronic fabrication of claim 10 wherein the patterned second dielectric layer is formed a dielectric material selected from the group consisting of silicon nitride dielectric material, silicon carbide dielectric materials, aluminum oxide dielectric material and titanium oxide dielectric materials.

16. The microelectronic fabrication of claim 10 further comprising over the substrate a third dielectric layer which covers the patterned second dielectric layer and in conjunction with the patterned second dielectric layer encapsulates the microelectronic device with respect to the patterned conductor layer, the third dielectric layer being formed from a third dielectric material having a third diffusion coefficient with respect to the conductor material from which is formed the patterned conductor layer, the third diffusion coefficient being less than the first diffusion coefficient.

17. The microelectronic fabrication of claim 10 further comprising forming over the substrate a second microelectronic device not annularly surrounded by the patterned second dielectric layer.

18. The microelectronic fabrication of claim 17 wherein the microelectronic device is employed within a memory circuit formed over the substrate and the second microelectronic device is