Method of copper interconnect formation using atomic layer copper deposition

• US 6,368,954 B1
• Filed: 07/28/2000
• Issued: 04/09/2002
• Est. Priority Date: 07/28/2000
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc., Aixtron Inc. (Aixtron AG)
• Original Assignee: Advanced Micro Devices, Inc., Genus PLC
• Inventors: Galewski, Carl, Lopatin, Sergey D., Nogami, Takeshi T. N.
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US09/627,352
• Time in Patent Office: 620 Days
• Field of Search: 438/627, 438/628, 438/629, 438/643, 438/637-638, 438/644, 438/653, 438/654, 438/674, 438/675, 438/678-681, 438/687
• US Class Current: 438/627
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 21/76876 for deposition from the gas phase, e.g. CVD
• CPC Class Codes: H01L 2221/1089 Stacks of seed layers

Abstract

A semiconductor interconnect structure having a substrate with an interconnect structure patterned thereon, a barrier layer, a pre-seed layer, a seed layer, a bulk interconnect layer, and a sealing layer. A process for creating such structures is described. The barrier layer is formed using atomic layer deposition techniques. Subsequently, a pre-seed layer is formed to create a heteroepitaxial interface between the barrier and pre-seed layers. This is accomplished using atomic layer epitaxy techniques to form the pre-seed layer. Thereafter, a seed layer is formed by standard deposition techniques to create a homoepitaxial interface between the seed and pre-seed layers. Upon this layered structure further bulk deposition of conducting materials is done. Excess material is removed from the bulk layer and a sealing layer is formed on top to complete the interconnect structure.

Claims

1. A method for forming interconnecting conductive lines and vias on a semiconductor substrate during a semiconductor fabrication process, comprising the steps of:

(a) providing a semiconductor substrate having an in-laid circuit pattern corresponding to a conductor wiring pattern, formed thereon;

(b) forming a barrier layer over said semiconductor surface, including said in-laid circuit pattern;

(c) forming a pre-seed layer over said barrier layer;

(d) forming a seed layer over said pre-seed layer;

(e) forming a bulk interconnect layer over said pre-seed layer; and

(f) subjecting said substrate to further processing.

2. The method, as recited in claim 1, wherein said step (b) of forming said barrier layer includes the step of forming said barrier layer by using atomic layer deposition.

3. The method, as recited in claim 2, wherein said barrier layer is formed using a material selected from the group consisting of TiN, WN, TaN, Ta, and the silicide compounds thereof.

4. The method, as recited in claim 2, wherein said barrier layer is constructed of a titanium nitride film formed using precursor materials which include TiCl₄ and NH₃.

5. The method, as recited in claim 2, wherein said barrier layer is constructed of a tungsten nitride film formed using precursor materials which include WF₆ and NH₃.

6. The method, as recited in claim 2, wherein said barrier layer is constructed of tungsten nitride film formed using precursor materials which include W(CO)₃ and NH₃.

7. The method, as recited in claim 2, wherein said barrier layer is constructed of tantalum nitride film formed using precursor materials which include TaCl₅ and NH₃.

8. The method, as recited in claim 2, wherein said step (c) of forming a pre-seed layer includes the step of forming said pre-seed layer by using atomic layer epitaxy.

9. The method, as recited in claim 8, wherein said pre-seed layer is formed using a highly conductive material.

10. The method, as recited in claim 8, wherein said pre-seed layer is formed essentially of copper.

11. The method, as recited in claim 10, wherein said copper pre-seed layer is formed using Cu(II)β

-diketonate precursor materials.

12. The method, as recited in claim 11, wherein said Cu(II)P-diketonate precursor materials are selected from the group consisting essentially of Cu(II)-2,2,6,6,-tetramethyl-3,5-heptandionate (Cu(thd)₂) and Cu(II)-1,1,1,5,5,5-hexafluro-2,4-pentanedionate (Cu(hfac)₂).

13. The method, as recited in claim 8, wherein the step (d) of forming said seed layer includes forming said seed layer by using a technique selected from a group consisting essentially of chemical vapor deposition and metal organic chemical vapor deposition.

14. The method, as recited in claim 13, wherein the step (d) of forming said seed layer includes forming a seed layer essentially comprising of copper.

15. The method, as recited in claim 14, wherein said step (d) of forming a seed layer includes using a Cu(I)β

-diketonate as a precursor for forming said copper seed layer.

16. The method, as recited in claim 8, wherein said step (e) of forming a said bulk interconnect layer includes forming said bulk interconnect layer by using a technique selected from a group consisting essentially of chemical vapor deposition and electroplating.

17. The method, as recited in claim 8, wherein said step (f) of subjecting said substrate to further processing includes the step of removing excess material from said bulk interconnect layer.

18. The method, as recited in claim 17, wherein said step (f) of removing excess material from said bulk interconnect layer comprises removing said excess material by using chemical mechanical polishing.

19. The method, as recited in claim 18, wherein said step (f) of subjecting said substrate to further processing includes forming a top sealing layer over said bulk interconnect layer.

20. A method for forming a seed layer on a semiconductor substrate during a semiconductor fabrication process, comprising the steps of:

(a) providing a semiconductor substrate having an in-laid circuit pattern formed thereon;

(b) forming a barrier layer over said semiconductor surface;

(c) forming a pre-seed layer over said barrier layer, creating an first interface between said pre-seed layer and said barrier layer; and

(d) forming a seed layer over said pre-seed layer, creating a second interface between said seed layer and said pre-seed layer.

21. The method, as recited in claim 20, wherein said step (c) of creating an first interface between said pre-seed layer and said barrier layer creates a heteroepitaxial interface.

22. The method, as recited in claim 21, wherein said step (c) of creating a second interface between said seed layer and said pre-seed layer creates a homoepitaxial interface.

23. The method, as recited in claim 22, wherein said step (b) of forming a barrier layer over said semiconductor surface comprises forming said barrier layer using atomic layer deposition techniques.

24. The method, as recited in claim 23, wherein said step (c) of forming a pre-seed layer comprises forming said pre-seed layer using atomic layer epitaxy techniques.

25. The method, as recited in claim 24, wherein said step (d) of forming a seed layer comprises forming said seed layer using a technique selected a group consisting essentially of chemical vapor deposition and metal organic chemical vapor deposition.

26. The method, as recited in claim 25, wherein said barrier layer is formed to a thickness in a range of about 20 to 300 Å

.

27. The method, as recited in claim 26, wherein said pre-seed layer is formed to a thickness in a range of about 1.5 to 10 Å

.

28. The method, as recited in claim 26, wherein said seed layer is formed to a thickness in a range of about 50 to 2000 Å

.