Semiconductor device and method of manufacturing the semiconductor device

• US 6,369,410 B1
• Filed: 12/15/1998
• Issued: 04/09/2002
• Est. Priority Date: 12/15/1997
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Fukunaga, Takeshi, Ohtani, Hisashi, Ohnuma, Hideto, Adachi, Hiroki, Yamazaki, Shunpei, Fujimoto, Etsuko
• Primary Examiner(s): Jackson, Jr., Jerome
• Application Number:
  US09/210,781
• Time in Patent Office: 1,211 Days
• Field of Search: 257/72, 257/751, 257/412, 257/761, 257/765, 257/766, 257/767, 345/92
• US Class Current: 257/72
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

A TFT using an aluminum material for a gate electrode is manufactured at a high yield factor. The gate electrode provided over an active layer and a gate insulating film is constituted by a lamination film of a tantalum layer and an aluminum layer. In this structure, the tantalum layer functions as a stopper, so that it is possible to prevent a constituent material of the aluminum layer from intruding into the gate insulating film. An end portion of the tantalum layer is transformed into tantalum oxide, which has an effect to lower damage at ion implantation to the gate insulating film in the formation of an LDD region.

Claims

1. A semiconductor device comprising a plurality of TFTs formed on a substrate, each of said TFTs comprising:

an active layer comprising at least a channel forming region, and source and drain regions;

a gate insulating film adjacent to said active layer; and

a gate electrode comprising a lamination of a tantalum layer and a conductive layer comprising aluminum or aluminum as its main ingredient,

wherein a tantalum oxide layer adjacent to the tantalum layer is formed adjacent to the gate insulating film and an end portion of said tantalum oxide layer is aligned with an end portion of said gate insulating film.

2. A device according to claim 1, wherein the tantalum layer has a thickness of 5 to 200 nm.

8. A device according to any one of claims 1, 3, 4, or 7, further comprising a nonporous alumina layer disposed on a surface of the conductive layer comprising aluminum or aluminum as its main ingredient.

9. A device according to any one of claims 1, 3, 4, or 7, wherein the active layer further comprises an LDD region, and the tantalum oxide layer is located over the LDD region.

10. A device according to claim 9, wherein the tantalum oxide layer has a thickness 2 to 4 times that of the tantalum layer.

31. A device according to claim 1, wherein the tantalum layer has an enough thickness to function as a blocking layer which prevents a constituent element of the conductive layer comprising aluminum or aluminum as its main ingredient from intruding into the gate insulating film.

3. A semiconductor device comprising a plurality of TFTs formed on a substrate, each of said TFTs comprising:

an active layer comprising at least a channel forming region, and source and drain regions;

a gate insulating film adjacent to said active layer; and

a gate electrode comprising a lamination of a tantalum layer and a conductive layer comprising aluminum or aluminum as its main ingredient,

wherein a tantalum oxide layer is adjacent to the tantalum layer at a region where the tantalum layer does not overlap with the conductive layer comprising aluminum or aluminum as its main ingredient.

5. A device according to claim 3 or 4, wherein the tantalum oxide layer is a layer obtained by anodic oxidation of a part of the tantalum layer.

6. A device according to claim 3 or 4, wherein the tantalum oxide layer has a thickness 2 to 4 times that of the tantalum layer.

4. A semiconductor device comprising a plurality of TFTs formed on a substrate, each of said TFTs comprising:

an active layer comprising at least a channel forming region, and source and drain regions;

a gate insulating film adjacent to said active layer; and

a gate electrode comprising a lamination of a tantalum layer and a conductive layer comprising aluminum or aluminum as its main ingredient,

wherein an end portion of the tantalum layer protrudes outside of the conductive layer comprising aluminum or aluminum as its main ingredient, and

wherein a tantalum oxide layer adjacent to the tantalum layer is formed adjacent to the gate insulating film and an end portion of said tantalum oxide layer is aligned with an end portion of said gate insulating film.

7. A semiconductor device comprising a plurality of TFTs formed on a substrate, each of said TFTs comprising:

an active layer comprising at least a channel forming region, and source and drain regions;

a gate insulating film formed on said active layer; and

a gate electrode comprising a lamination of a tantalum layer and a conductive layer comprising aluminum or aluminum as its main ingredient,

wherein an end portion of the tantalum layer protrudes outside of the conductive layer comprising aluminum or aluminum as its main ingredient, and

wherein a tantalum oxide layer adjacent to the tantalum layer is formed on the gate insulating film and an end portion of said tantalum oxide layer is aligned with an end portion of said gate insulating film.

11. A semiconductor device having a plurality of TFTs formed on a substrate, each of the TFTs comprising:

an active layer comprising at least a channel forming region, and source and drain regions;

a gate insulating film adjacent to said active layer; and

a gate electrode comprising a lamination of a valve metal layer and a conductive layer,

wherein an oxide layer of the valve metal layer is adjacent to said gate insulating film and end portion of said oxide layer of the valve metal layer is aligned with an end portion of the gate insulating film.

12. A device according to claim 11, wherein the valve metal layer has a thickness of 5 to 200 nm.

13. A device according to claim 11, wherein the valve metal layer is selected from the group consisting of Ta, Nb, Hf, Ti, Cr, alloys of those metal elements, and an alloy of Mo and Ta.

32. A device according to claim 11, wherein the conductive layer comprises aluminum.

14. A semiconductor device having a plurality of TFTs formed on the same substrate, each of the TFTs comprising:

an active layer comprising at least a channel forming region, and source and drain regions;

a gate insulating film adjacent to said active layer; and

a gate electrode comprising a lamination of a valve metal layer and a conductive layer,

wherein an oxide layer of the valve metal layer is located at a region where the valve metal layer does not overlap with the conductive layer, and

wherein end portion of said oxide layer of the valve metal layer is aligned with an end portion of the gate insulating film.

15. A device according to claim 14, wherein the valve metal is selected from the group consisting of Ta, Nb, Hf, Ti, Cr, alloys of those metal elements, and an alloy of Mo and Ta.

16. A device according to claim 14, wherein the oxide layer of the valve metal layer is a layer obtained by anodic oxidation of a part of the valve metal layer.

17. A device according to claim 14, wherein the oxide layer of the valve metal layer has a thickness 2 to 4 times that of the valve metal layer.

18. A device according to claim 14, further comprising an oxide layer of the conductive layer located on a surface of the conductive layer.

19. A device according to claim 14, wherein the active layer further comprises an LDD region, and the oxide layer of the valve metal layer is located over the LDD region.

33. A device according to claim 14, wherein the conductive layer comprises aluminum.

20. A semiconductor device having a plurality of TFTs formed on a substrate, each of the TFTs comprising:

an active layer comprising at least a channel forming region, and source and drain regions;

a gate insulating film adjacent to said active layer; and

a gate electrode comprising a lamination of a valve metal layer and a conductive layer comprising aluminum or aluminum as its main ingredient,

wherein an end portion of the valve metal layer protrudes outside of the conductive layer comprising aluminum or aluminum as its main ingredient, and an oxide layer of the valve metal layer is formed adjacent to said gate insulating film, and

wherein end portion of said oxide layer of the valve metal layer is aligned with an end portion of the gate insulating film.

21. A device according to claim 20, wherein the valve metal layer is selected from the group consisting of Ta, Nb, Hf, Ti, Cr, alloys of those metal elements, and an alloy of Mo and Ta.

22. A device according to claim 20, wherein the oxide layer of the valve metal layer is a layer obtained by anodic oxidation of a part of the valve metal layer.

23. A device according to claim 20, wherein the oxide layer of the valve metal layer has a thickness 2 to 4 times that of the valve metal layer.

24. A device according to claim 20, further comprising a nonporous alumina layer disposed on a surface of the conductive layer comprising aluminum or aluminum as its main ingredient.

25. A device according to claim 20, wherein the active layer further comprises an LDD region, and the oxide layer of the valve metal layer is located over the LDD region.

26. A semiconductor device having a plurality of TFTs formed on a substrate, each of the TFTs comprising:

an active layer comprising at least a channel forming region, and source and drain regions;

a gate insulating film formed on said active layer; and

a gate electrode comprising a lamination of a valve metal layer and a conductive layer,

wherein an end portion of the valve metal layer protrudes outside of the conductive layer, and

wherein an oxide layer of the valve metal layer is located on said gate electrode; and

wherein end portion of said oxide layer of the valve metal layer is aligned with an end portion of the gate insulating film.

27. A device according to claim 26, wherein the valve metal layer is selected from the group consisting of Ta, Nb, Hf, Ti, Cr, alloys of those metal elements, and an alloy of Mo and Ta.

28. A device according to claim 26, further comprising an oxide layer of the conductive layer located on a surface of the conductive layer.

29. A device according to claim 26, wherein the active layer further comprises an LDD region, and the oxide layer of the valve metal layer is located over the LDD region.

30. A device according to claim 26, wherein the oxide layer of the valve metal layer has a thickness 2 to 4 times that of the valve metal layer.

34. A device according to claim 26, wherein the conductive layer comprises aluminum.