Semiconductor device with a thin gate stack having a plurality of insulating layers

• US 6,369,423 B2
• Filed: 03/03/1998
• Issued: 04/09/2002
• Est. Priority Date: 03/03/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc., Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: International Business Machines Corporation, Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Shiozawa, Jun-ichi, Okumura, Katsuya, Gambino, Jeffrey P., Ohiwa, Tokuhisa
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Doan, Theresa T.
• Application Number:
  US09/033,899
• Publication Number:
  US 20020014657A1
• Time in Patent Office: 1,498 Days
• Field of Search: 257/327, 257/338, 257/369, 257/635, 257/750, 257/332, 257/319, 257/774, 257/306, 257/324, 257/326, 438/180, 438/182, 438/672, 438/675, 438/624, 438/639, 438/253, 438/258
• US Class Current: 257/327
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

The present invention intends to provide a semiconductor device capable of realizing a thin gate stack and the manufacturing method thereof. A gate cap layer and/or a protection insulating film (an etching stopper) has a plurality of insulating materials such as oxide and nitride stacked on each other. With this structure, an insulating layer having an etching rate lower than that of the interlayer insulating layer, for example, can be exposed during the etching of the interlayer insulating layer, and the gate stack can be formed thin and the aspect ratio of the contact hole formed in the device can be reduced. The present invention can realize a thin gate stack in such a manner, and thus is suitable for a SAC used in a DRAM.

Claims

1. A semiconductor device with a thin gate stack including a plurality of insulating layers and a contact hole formed through the gate stack, comprising:

a substrate;

a gate oxide film formed selectively on the substrate;

a gate electrode formed on the gate oxide film;

a gate cap layer formed as an etching stopper on the gate electrode, and not extending over sidewalls of the gate electrode, the gate cap layer including a plurality of insulating layers;

a protection insulating film formed on the gate cap layer and the sidewalls of the gate electrode; and

a diffusion layer formed on a surface of the substrate so as to contact with a channel forming region formed below the gate electrode, the diffusion layer being located at a bottom of the contact hole

wherein an etching rate of one of the insulating layers in the gate cap layer is lower than an etching rate of the protection insulating film.

2. A semiconductor device according to claim 1, wherein the gate cap layer has a nitride layer formed on the gate electrode and an oxide layer formed on the nitride layer.

3. A semiconductor device according to claim 1 wherein a surface of the gate cap layer adjacent the contact hole is narrower in width than the gate electrode.

4. A semiconductor device according to claim 1, further comprising:

a wiring layer formed in contact with a surface of the diffusion layer, one of sidewalls of the protection insulating film and one of upper comers of the gate cap layer.

5. A semiconductor device with a thin gate stack including a plurality of insulating layers and a contact hole formed through the gate stack, comprising:

a substrate;

a gate oxide film formed selectively on the substrate;

a gate electrode formed on the gate oxide film;

a gate cap layer formed as an etching stopper on the gate electrode, and not extending over sidewalls of the gate electrode, the gate cap layer including a plurality of insulating layers;

a protection insulating film formed as an etching stopper on a surface of the gate cap layer, a portion of sidewalls of the gate cap layer and said sidewalls of the gate electrode, the protection insulating film including a plurality of insulating layers; and

a diffusion layer formed on a surface of the substrate so as to contact with a channel forming region formed below the gate electrode, the diffusion layer being located at a bottom of the contact hole

wherein an etching rate of an upper layer in the insulating layers of the gate cap layer is lower than an etching rate of an under layer in the insulating layers of the protection insulating film.

6. A semiconductor device according to claim 5, wherein the protection insulating film has a nitride layer formed on the gate cap layer and an oxide layer formed on the nitride layer, the oxide layer being thinner than the nitride layer, and the gate cap layer has a nitride layer formed on the gate electrode and an oxide layer formed on the nitride layer.

7. A semiconductor device according to claim 5, wherein the protection insulating film is thinner than the gate cap layer.

8. A semiconductor device according to claim 7, wherein a surface of the gate cap layer adjacent the contact hole is narrower in width than the gate electrode.

9. A semiconductor device according to claim 8, further comprising:

a wiring layer formed in contact with a surface of the diffusion layer, one of sidewalls of the protection insulating film and one of upper corners of the gate cap layer.

10. A semiconductor device according to claim 9, wherein the protection insulating film has a nitride layer formed on the gate cap layer and an oxide layer formed on the nitride layer, and the gate cap layer has a nitride layer formed on the gate electrode and an oxide layer formed on the nitride layer.

11. A semiconductor device according to claim 5, wherein a surface of the gate cap layer adjacent the contact hole is narrower in width than the gate electrode.

12. A semiconductor device according to claim 5, further comprising:

a wiring layer formed in contact with a surface of the diffusion layer, one of sidewalls of the protection insulating film and one of upper corners of the gate cap layer.

13. A semiconductor device with a thin gate stack including a plurality of insulating layers and a contact hole formed through the gate stack, comprising:

a substrate;

a gate oxide film formed selectively on the substrate;

a first gate electrode formed on the gate oxide film;

a first gate cap layer formed as an etching stopper on the first gate electrode, and not extending over sidewalls of the first gate electrode, the first gate cap layer including a plurality of insulating layers;

a first protection insulating film formed on a surface of the first gate cap layer, a portion of sidewalls of the first gate cap layer and sidewalls of the first gate electrode;

a second gate electrode formed on a region of the gate oxide different from that of the first gate electrode;

a second gate cap layer formed as an etching stopper on the second gate electrode, and not extending over sidewalls of the second gate electrode, the second gate cap layer including a plurality of insulating layers;

a second protection insulating film formed on a surface of the second gate cap layer, a portion of sidewalls of the second gate cap layer and sidewalls of the second gate electrode;

a diffusion layer formed on a surface of the substrate so as to contact with a channel forming region formed below the first gate electrode and the second gate electrode, the diffusion layer being located at a bottom of the contact hole; and

a wiring layer arranged in the contact hole in between the first gate electrode and the second gate electrode, the wiring layer being formed in contact with a surface of the diffusion layer, one of sidewalls of the first protection insulating film and one of sidewalls of the second protection insulating film

wherein an etching rate of one of the insulating layers in the first gate gap layer is lower than an etching rate of the first protection insulating film, and an etching rate of one of the insulating layers in the second gate cap layer is lower than an etching rate of the second protection insulating film.

14. A semiconductor device according to claim 13, wherein the first and second gate cap layers have nitride layers formed on the first and second gate electrodes and oxide layers formed on the nitride layers.

15. A semiconductor device according to claim 14, wherein each of the first and second protection insulating films is thinner than each of the first and second gate cap layers.

16. A semiconductor device according to claim 15, wherein each of surfaces of the first and second gate cap layers adjacent the contact hole is narrower in width than each of the first and second gate electrodes.

17. A semiconductor device according to claim 13, wherein each of the first and second protection insulating films is thinner than each of the first and second gate cap layers.

18. A semiconductor device according to claim 13, wherein each of surfaces of the first and second gate cap layers adjacent the contact hole is narrower in width than each of the first and second gate electrodes.

19. A semiconductor device with a thin gate stack including a plurality of insulating layers and a contact hole formed through the gate stack, comprising:

a substrate;

a gate oxide film formed selectively on the substrate;

a first gate electrode formed on the gate oxide film;

a first gate cap layer formed as an etching stopper on the first gate electrode, wherein the first gate cap layer is not in contact with sidewalls of the first gate electrode, the first gate cap layer including a plurality of insulating layers;

a first protection insulating film formed as an etching stopper on a surface of the first gate cap layer, a portion of sidewalls of the first gate cap layer and sidewalls of the first gate electrode, the first protection insulating film including a plurality of insulating films;

a second gate electrode formed on a region of the gate oxide different from that of the first gate electrode;

a second gate cap layer formed as an etching stopper on the second gate electrode, wherein the second gate cap layer is not in contact with sidewalls of the second gate electrode, the second gate cap layer including a plurality of insulating layers;

a second protection insulating film formed as an etching stopper on a surface of the second gate cap layer, a portion of sidewalls of the second gate cap layer and sidewalls of the second gate electrode, the second protection insulating film including a plurality of insulating films;

a diffusion layer formed on a surface of the substrate so as to contact with a channel forming region formed below the first gate electrode and the second gate electrode, the diffusion layer being located at a bottom of the contact hole; and

a wiring layer arranged in the contact hole in between the first gate electrode and the second gate electrode, the wiring layer being formed in contact with a surface of the diffusion layer, one of sidewalls of the first protection insulating film and one of sidewalls of the second protection insulating film;

wherein an etching rate of an upper layer in the insulating layers of the first gate gap layer is lower than an etching rate of an under layer in the insulating layers of the first protection insulating film, and an etching rate of an upper layer in the insulating layers of the second gate cap layer is lower than an etching rate of an under layer in the insulating layers of the second protection insulating film.

20. A semiconductor device according to claim 19, wherein the first and second protection insulating films have nitride layers formed on the first and second gate cap layers and oxide layers formed on the nitride layers, each of the oxide layers being thinner than each of the nitride layers, and the first and second gate cap layers have nitride layers formed on the first and second gate electrodes and oxide layers formed on the nitride layers.

21. A semiconductor device according to claim 20, wherein each of the first and second protection insulating films is thinner than each of the first and second gate cap layers.

22. A semiconductor device according to claim 21, wherein each of the surfaces of the first and second gate cap layers adjacent the contact hole is narrower in width than each of the first and second gate electrodes.

23. A semiconductor device according to claim 19, wherein each of the first and second protection insulating films is thinner than each of the first and second gate cap layers.

24. A semiconductor device according to claim 19, wherein each of the surfaces of the first and second gate cap layers adjacent the contact hole is narrower in width than each of the first and second gate electrodes.

25. A semiconductor device with a thin gate stack including a plurality of insulating layers and a contact hole formed through the gate stack, comprising:

a substrate;

a gate oxide film formed selectively on the substrate;

a gate electrode formed on the gate oxide film;

a gate cap layer formed as an etching stopper on the gate electrode, and not extending over sidewalls of the gate electrode, the gate cap layer including a plurality of insulating layers, the gate cap layer having a nitride layer formed on the gate electrode, an oxide layer formed on the nitride layer and another nitride layer formed on the oxide layer;

a protection insulating film formed on the gate cap layer and the sidewalls of the gate electrode, the protection insulating film being made of a nitride; and

a diffusion layer formed on a surface of the substrate so as to contact with a channel forming region formed below the gate electrode, the diffusion layer being located at a bottom of the contact hole;

wherein an etching rate of the oxide layer in the gate cap layer is lower than that of the protection insulating film.

26. A semiconductor device with a thin gate stack including a plurality of insulating layers and a contact hole formed through the gate stack, comprising:

a substrate;

a gate oxide film formed selectively on the substrate;

a gate electrode formed on the gate oxide film;

a gate cap layer formed as an etching stopper on the gate electrode, and not extending over sidewalls of the gate electrode, the gate cap layer including a plurality of insulating layers, the gate cap layer having a nitride layer formed on the gate electrode and an oxide layer formed on the nitride layer;

a protection insulating film formed as an etching stopper on a surface of the gate cap layer, a portion of sidewalls of the gate cap layer and said sidewalls of the gate electrode, the protection insulating film including a plurality of insulating layers, the protection insulating film having a nitride layer formed on the gate cap layer and an oxide layer formed on the nitride layer; and

a diffusion layer formed on a surface of the substrate so as to contact with a channel forming region formed below the gate electrode, the diffusion layer located at a bottom of the contact hole;

wherein an etching rate of the oxide layer in the gate cap layer is lower than that of the nitride layer in the protection insulating film.

27. A semiconductor device with a thin gate stack including a plurality of insulating layers and a contact hole formed through the gate stack, comprising:

a substrate;

a gate oxide film formed selectively on the substrate;

a first gate electrode formed on the gate oxide film;

a first gate cap layer formed as an etching stopper on the first gate electrode, and not extending over sidewalls of the first gate electrode, the first gate cap layer including a plurality of insulating layers, the first gate gap layer having a nitride layer formed on the gate electrode, an oxide layer formed on the nitride layer and another nitride layer formed on the oxide layer;

a first protection insulating film formed on a surface of the first gate cap layer, a portion of sidewalls of the first gate cap layer and said sidewalls of the first gate electrode, the first protection insulating film is made of a nitride;

a second gate electrode formed on a region of the gate oxide different from that of the first gate electrode;

a second gate cap layer as an etching stopper formed on the second gate electrode, and not extending over sidewalls of the second gate electrode, the second gate cap layer including a plurality of insulating layers, the second gate gap layer having a nitride layer formed on the gate electrode, an oxide layer formed on the nitride layer and another nitride layer formed on the oxide layer;

a second protection insulating film formed on a surface of the second gate cap layer, a portion of sidewalls of the second gate cap layer and sidewalls of the second gate electrode, the second protection insulating film is made of a nitride;

a diffusion layer formed on a surface of the substrate so as to contact with a channel forming region formed below the first gate electrode and the second gate electrode, the diffusion layer being located at a bottom of the contact hole; and

a wiring layer arranged in the contact hole between the first gate electrode and the second gate electrode, the wiring layer being formed in contact with a surface of the diffusion layer, one of sidewalls of the first protection insulating film and one of sidewalls of the second protection insulating film, one of upper comers of the oxide layer in the first gate cap layer and one of upper comers of the oxide layer in the second gate cap layer;

wherein an etching rate of the oxide layer in the first gate cap layer is lower than that of the first protection insulating film, and an etching rate of the oxide layer in the second gate cap layer is lower than that of the second protection insulating film.

28. A semiconductor device with a thin gate stack including a plurality of insulating layers and a contact hole formed through the gate stack, comprising:

a substrate;

a gate oxide film formed selectively on the substrate;

a first gate electrode formed on the gate oxide film;

a first gate cap layer formed as an etching stopper on the first gate electrode, wherein the first gate cap layer is not in contact with sidewalls of the first gate electrode, the first gate cap layer including a plurality of insulating layers, the gate gap layer having a nitride layer formed on the gate electrode and an oxide layer formed on the nitride layer;

a first protection insulating film formed as an etching stopper on a surface of the first gate cap layer, a portion of sidewalls of the first gate cap layer and sidewalls of the first gate electrode, the first protection insulating film including a plurality of insulating films, the first protection insulating film having a nitride layer formed on the first gate cap layer and an oxide layer formed on the nitride layer;

a second gate electrode formed on a region of the gate oxide different from that of the first gate electrode;

a second gate cap layer formed as an etching stopper on the second gate electrode, wherein the second gate cap layer is not in contact with sidewalls of the second gate electrode, the second gate cap layer including a plurality of insulating layers, the gate cap layer having a nitride layer formed on the gate electrode and an oxide layer formed on the nitride layer;

a second protection insulating film formed as an etching stopper on a surface of the second gate cap layer, a portion of sidewalls of the second gate cap layer and sidewalls of the second gate electrode, the second protection insulating film including a plurality of insulating films, the second protection insulating film having a nitride layer formed on the second gate cap layer and an oxide layer formed on the nitride layer;

a diffusion layer formed on a surface of the substrate so as to contact with a channel forming region formed below the first gate electrode and the second gate electrode, the diffusion layer being located at a bottom of the contact hole; and

a wiring layer arranged in the contact hole between the first gate electrode and the second gate electrode, the wiring layer being formed in contact with a surface of the diffusion layer, one of sidewalls of the first protection insulating film and one of sidewalls of the second protection insulating film, one of upper corners of the oxide layer in the first gate cap layer and one of upper coeners of the oxide layer in the second gate cap layer;

wherein an etching rate of the oxide layer in the first gate cap layer is lower than that of the nitride layer in the first protection insulating film, and an etching rate of the oxide layer in the second gate cap layer is lower than that of the nitride layer in the second protection insulating film.