Bias network for high efficiency RF linear power amplifier

• US 6,369,656 B2
• Filed: 07/02/2001
• Issued: 04/09/2002
• Est. Priority Date: 12/20/1999
• Status: Expired due to Term

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Dening, David C., Jorgenson, Jon D.
• Primary Examiner(s): Shingleton, Michael B
• Application Number:
  US09/897,260
• Publication Number:
  US 20010040482A1
• Time in Patent Office: 281 Days
• Field of Search: 330/296, 330/288, 330/285, 330/289
• US Class Current: 330/296
• CPC Class Codes: H03F 1/302 in bipolar transistor amplifiers H03F1/303, H03F1/305, H03F1/307 take precedence
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal

Abstract

A bias network uses resistive biasing, active biasing and current mirror biasing in combination to enhance RF power amplifier linearity and efficiency by forming a bias network that provides temperature compensation, minimizes current drain requirements for the Vbias source and reduces the level of RF linear amplifier quiescent current.

Claims

1. A linear amplifier bias network comprising:

a radio frequency bipolar junction transistor having a base, collector and emitter;

a capacitor having one end coupled to the base of the bipolar junction transistor and having an opposite end configured to receive a radio frequency input signal;

a ground node;

a second bipolar junction transistor having a base, a collector and emitter, wherein the emitter of the second bipolar junction transistor is coupled to the ground node;

a first resistor having one end coupled to a bias voltage source and further having a second end coupled to the base of the radio frequency bipolar junction transistor;

a second resistor having one end coupled to the base of the second bipolar junction transistor and having an opposite end coupled to the second end of the first resistor; and

a third resistor having one end coupled to the collector of the second bipolar junction transistor and having an opposite end coupled to the second end of the first resistor;

wherein a combination of resistance values for the first, second and third resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current and minimize gain expansion associated with the radio frequency bipolar junction transistor.

2. The linear amplifier bias network according to claim 1 further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the emitter of the second bipolar junction transistor such that the emitter of the second bipolar junction transistor is coupled to the ground node solely through the inductor.

3. The linear amplifier bias network according to claim 2 further comprising:

a third bipolar junction transistor having a base, collector and emitter, wherein the collector of the third bipolar junction transistor is coupled to a dc supply voltage;

a fourth resistor having a first end coupled to the emitter of the third bipolar junction transistor and having a second end coupled to the second end of the first resistor; and

a fifth resistor having a first end coupled to the base of the third bipolar junction transistor and having an opposite end coupled to the bias voltage supply;

wherein a combination of resistance values for the first, second, third, fourth and fifth resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current and minimize gain expansion associated with the radio frequency bipolar junction transistor.

4. The linear amplifier bias network according to claim 3 wherein any single resistor selected from the group consisting of the first, second, third, fourth and fifth resistors is configured to have zero resistance.

5. The linear amplifier bias network according to claim 2 wherein the bias voltage source comprises a resistor/diode network coupled to a supply voltage and configured to generate a desired reference supply voltage.

6. The linear amplifier bias network according to claim 2 wherein the bias voltage source comprises:

a diode network having a first node and a second node; and

a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the diode network first node such that a predetermined voltage drop is achieved across the diode network relative to the ground node to produce a desired bias voltage for the linear amplifier bias network.

7. The linear amplifier bias network according to claim 6 wherein the diode network includes at least one series resistor.

8. The linear amplifier bias network according to claim 7 further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the diode network such that a portion of the diode network is coupled to the ground node solely through the inductor.

9. The linear amplifier bias network according to claim 8 wherein any single resistor selected from the group consisting of the first, second and third resistors is configured to have zero resistance.

10. The linear amplifier bias network according to claim 2 wherein the bias voltage source comprises:

a transistor network configured as a diode network; and

a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the transistor network such that a predetermined voltage drop is achieved across the transistor network relative to the ground node to produce a desired supply reference voltage for the linear amplifier bias network.

11. The linear amplifier bias network according to claim 10 wherein the transistor network includes a series resistor.

12. The linear amplifier bias network according to claim 11 further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the transistor network such that a portion of the transistor network is coupled to the ground node solely through the inductor.

13. The linear amplifier bias network according to claim 12 wherein any single resistor selected from the group consisting of the first, second and third resistors is configured to have zero resistance.