Clock recovery system using wide-bandwidth injection locked oscillator with parallel phase-locked loop
First Claim
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1. A clock recovery system comprising:
- a source of a data signal;
an injection-locked oscillator, coupled to the data signal source, having a free-running frequency and generating a clock signal; and
a phase locked loop, coupled in parallel with the injection locked oscillator, and generating a control signal adjusting the free running frequency of the injection locked oscillator as a function of the clock signal and the data signal.
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Abstract
A clock recovery system includes a source of a data signal, and a free-running frequency adjustment circuit. The free-running frequency adjustment circuit includes an injection-locked oscillator having a free-running frequency and generating a clock signal and a phase locked loop, coupled in parallel with the injection locked oscillator, and generating a control signal adjusting the free running frequency of the injection locked oscillator.
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Citations
5 Claims
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1. A clock recovery system comprising:
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a source of a data signal;
an injection-locked oscillator, coupled to the data signal source, having a free-running frequency and generating a clock signal; and
a phase locked loop, coupled in parallel with the injection locked oscillator, and generating a control signal adjusting the free running frequency of the injection locked oscillator as a function of the clock signal and the data signal. - View Dependent Claims (2, 3, 4, 5)
the injection locked oscillator includes an injection input terminal coupled to the data signal source, an output terminal generating the clock signal, and a free running frequency adjustment terminal;
the phase locked loop comprises;
a phase comparator having a first input terminal coupled to the data signal source, a second input terminal coupled to the output terminal of the injection locked oscillator, and an output terminal generating a phase error signal; and
a loop filter having an input terminal coupled to the output terminal of the phase comparator and an output terminal coupled to the free running frequency adjustment terminal.
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4. The system of claim 3 wherein the loop filter comprises an integrator.
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5. The system of claim 2 wherein the phase locked loop is fabricated to have a relatively narrow bandwidth.
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