Circuit and method for preventing runaway in a phase lock loop

• US 6,369,660 B1
• Filed: 10/27/1999
• Issued: 04/09/2002
• Est. Priority Date: 10/27/1999
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Wei, Sen-Jung, Chen, Kuang-Yu
• Primary Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US09/428,624
• Time in Patent Office: 895 Days
• Field of Search: 331/11, 331/17, 331/1.A, 331/16, 375/376, 327/156, 327/159
• US Class Current: 331/15
• CPC Class Codes: H03L 7/102 the additional signal being directly applied to the controlled loop oscillator
• CPC Class Codes: H03L 7/105 Resetting the controlled oscillator when its frequency is outside a predetermined limit
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A circuit and/or method comprising an oscillator circuit, a pulse detection circuit and a control circuit. The oscillator circuit may be configured to generate an output signal having a frequency in response to (i) a first control signal and (ii) a second control signal. The pulse detection circuit may be configured to generate a detect signal in response to the output signal. The control circuit may be configured to generate the second control signal in response to said detect signal.

Claims

1. An apparatus comprising:

an oscillator circuit configured to generate an output signal having a frequency in response to (i) a first control signal generated in response to a reference signal and said output signal and (ii) a second control signal;

a pulse detection circuit comprising an edge detector circuit, configured to generate a detect signal in response to said output signal by detecting edges in a feedback signal; and

a control circuit configured to generate said second control signal in response to said detect signal by timing the spacing of said edges.

2. The apparatus according to claim 1, wherein said apparatus is part of a phase lock loop circuit.

7. The apparatus according to claim 1, wherein said oscillator circuit comprises a voltage controlled oscillator.

8. The apparatus according to claim 7, wherein said control circuit limits the maximum frequency of said voltage controlled oscillator.

9. The apparatus according to claim 1, wherein said detect signal is generated in response to a feedback signal from a feedback divider.

3. An apparatus comprising:

an oscillator circuit configured to generate an output signal having a frequency in response to (i) a first control signal and (ii) a second control signal;

a pulse detection circuit comprising an integrator and a hysteresis circuit, configured to generate a detect signal in response to said output signal by detecting edges in a feedback signal; and

a control circuit configured to generate said second control signal in response to said detect signal by timing the spacing of said edges.

4. The apparatus according to claim 3, wherein said hysteresis circuit comprises a schmitt trigger.

5. The apparatus according to claim 3, wherein said integrator circuit comprises a transistor, a resistor of known value, and a capacitor of known value.

6. The apparatus according to claim 5, wherein said resistor comprises one or more transistors.

10. An apparatus comprising:

means for generating an output signal having a frequency in response to (i) a first control signal generated in response to a reference signal and said output signal and (ii) a second control signal;

means for generating a detect signal, comprising an edge detector circuit, in response to said output signal by detecting edges in a feedback signal; and

means for generating said second control signal in response to said detect signal by timing the spacing of said edges.

11. A method of preventing a runaway condition in a phase lock loop comprising the steps of:

(A) generating an output signal having a frequency in response to (i) a first control signal and (ii) a second control signal;

(B) generating a detect signal in response to said output signal by (i) detecting edges in a feedback signal and (ii) timing the spacing of said edges; and

(C) generating said second control signal in response to said detect signal.

12. The method according to claim 11, wherein said step of detecting edges in said feedback signal further comprises the sub-steps of:

(B-i-a) generating a time-delayed version of said feedback signal;

(B-i-b) comparing said time delayed version of said feedback signal to said input signal;

(B-i-c) if said time-delayed version of said feedback signal and said feedback signal are in a first predetermined state, generating an edge detect signal having a first logic state;

(B-i-d) if said time-delayed version of said feedback signal and said feedback signal are in a second predetermined state, generating said edge detect signal having a second logic state;

(B-i-e) if said time-delayed version of said feedback signal and said feedback signal are in different states, generating said edge detect signal having said second logic state.

13. The method according to claim 11, wherein said feedback signal is generated by a feedback divider in response to said output signal.

14. The method according to claim 11, further comprising a step of (d) limiting the frequency of said output signal in response to said second control signal.