Intra-pixel frame storage element, array, and electronic shutter method suitable for electronic still camera applications

• US 6,369,853 B1
• Filed: 11/13/1997
• Issued: 04/09/2002
• Est. Priority Date: 11/13/1997
• Status: Expired due to Term

• Current Assignee: Foveon, Inc. (Avis Budget Group Incorporated)
• Original Assignee: Foveon, Inc. (Avis Budget Group Incorporated)
• Inventors: Merrill, Richard B., Turner, Richard M., Lyon, Richard F., Mead, Carver A.
• Primary Examiner(s): Garber, Wendy R.
• Assistant Examiner(s): Vu, Ngoc-Yen, VU, NGOC YEN T
• Application Number:
  US08/969,383
• Time in Patent Office: 1,608 Days
• Field of Search: H04/N.314, 250/208.1, 257/223, 257/229, 257/230-233, 257/257, 257/258, 257/290, 257/291, 257/444, 257/445, 348/302-304, 348/307-310
• US Class Current: 348/302
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H04N 25/53 Control of the integration time
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/771 comprising storage means other than floating diffusion

Abstract

A storage pixel sensor disposed on a semiconductor substrate comprises a capacitive storage element having a first terminal connected to a fixed potential and a second terminal. A photodiode has an anode connected to a first potential and a cathode. A semiconductor reset switch has a first terminal connected to the cathode and a second terminal connected to a reset potential. A semiconductor transfer switch has a first terminal connected to the cathode and a second terminal connected to the second terminal of the capacitive storage element. A semiconductor amplifier has an input connected to the capacitive storage element and an output. The semiconductor reset switch and the semiconductor transfer switch each have a control element connected to a control circuit for selectively activating the semiconductor reset switch and the semiconductor transfer switch. A light shield is disposed over portions of the semiconductor substrate comprising a circuit node including the second terminal of the semiconductor transfer switch, the second terminal of the capacitive storage element and the input of the semiconductor amplifier and to prevent substantially all photons from entering the circuit node. Structures are present for preventing substantially all minority carriers generated in the semiconductor substrate from entering the circuit node. A plurality of storage pixel sensors are disposed in an array.

Claims

1. A storage pixel sensor disposed on a semiconductor substrate comprising:

a capacitive storage element having a first terminal connected to a fixed potential and a second terminal;

a photodiode having a first terminal connected to a first potential and a second terminal;

a semiconductor reset switch having a first terminal connected to said second terminal of said photodiode and a second terminal connected to a reset potential that reverse biases said photodiode;

a semiconductor transfer switch having a first terminal connected to said second terminal of said photodiode and a second terminal connected to said second terminal of said capacitive storage element;

a semiconductor amplifier having an input connected to said second terminal of said capacitive storage element and an output;

said semiconductor reset switch and said semiconductor transfer switch each having a control element connected to a control circuit for selectively activating said semiconductor reset switch and said semiconductor transfer switch;

a light shield disposed over portions of the semiconductor substrate comprising a circuit node including said second terminal of said semiconductor transfer switch, said second terminal of said capacitive storage element and said input of said semiconductor amplifier and to prevent substantially all photons from entering said circuit node; and

minority carrier rejection means for preventing substantially all minority carriers generated in said semiconductor substrate from entering said circuit node.

2. The storage pixel sensor of claim 1, further including a semiconductor select switch having an input connected to the output of said amplifier, an output connected to an output bus, and a control element connected to said control circuit.

3. The storage pixel sensor of claim 1 wherein:

said semiconductor substrate is formed from a semiconductor material of a first conductivity type;

said light shield is a portion of a metal interconnect layer disposed over said semiconductor substrate;

said semiconductor transfer switch comprises a MOS transistor of a second conductivity type opposite said first conductivity type, said MOS transistor formed in a well of said first conductivity type, said well disposed in said semiconductor substrate, wherein said minority carrier rejection means comprises said well.

4. The storage pixel sensor of claim 1 wherein:

said semiconductor substrate is formed from a semiconductor material of a first conductivity type;

said light shield is a portion of a metal interconnect layer disposed over said semiconductor substrate;

said semiconductor transfer switch comprises a MOS transistor of said first conductivity type formed in a well of a second conductivity type opposite said first conductivity type, said well disposed in said semiconductor substrate, wherein said minority carrier rejection means comprises said well.

5. The storage pixel sensor of claim 1 wherein:

said semiconductor substrate is p-type semiconductor substrate;

said light shield is a portion of a metal interconnect layer disposed over said semiconductor substrate;

said semiconductor transfer switch comprises an N-Channel MOS transistor formed in a p-well formed in said p-type semiconductor substrate, wherein said minority carrier rejection means comprises said p-well.

6. The storage pixel sensor of claim 1 wherein:

said semiconductor substrate is p-type semiconductor substrate;

said light shield is a portion of a metal interconnect layer disposed over said semiconductor substrate;

said semiconductor transfer switch each comprise a P-Channel MOS transistor formed in an n-well formed in said p-type semiconductor substrate, wherein said minority carrier rejection means comprises said n-well.

7. A method for operating a storage pixel sensor of claim 1 including the steps of:

(1) turning on the transfer switch of the storage pixel sensor for a first time period and turning off said transfer switch at the end of said first time period;

(2) turning on the reset switch of the storage pixel sensor for a reset period occurring during a first portion of said first time period and turning off said reset switch at the end of said first portion of said first time period;

(3) integrating photocurrent in the storage pixel sensor for an integration period occurring during a second portion of said first time period after said reset switch has been turned off, said integration period ending at the end of said first time period;

(4) turning on the reset switch of the storage pixel sensor after the end of said first time period; and

(5) reading an output signal from the amplifier of the storage pixel sensor.

8. A method for operating the storage pixel sensor of claim 1, including the steps of:

(1) turning on the transfer switch of the storage pixel sensor for a first time period and turning off said transfer switch at the end of said first time period;

(2) turning on the reset switch of the storage pixel sensor for a reset period occurring during a first portion of said first time period and turning off said reset switch at the end of said first portion of said first time period;

(3) integrating photocurrent in the storage pixel sensor for an integration period occurring during a second portion of said first time period after said reset switch has been turned off, said integration period ending at the end of said first time period;

(4) turning on the reset switch of the storage pixel sensor for a reference period after the end of said first time period; and

(5) reading an output signal from the storage pixel sensor, then activating the transfer switch of the storage pixel sensor and reading a reference signal from the storage pixel sensor, then taking the difference between the output signal and the reference signal for the storage pixel sensor.

9. A method for operating an array of storage pixel sensors of claim 1 arranged in rows, including the steps of:

(1) turning on the transfer switches of all storage pixel sensors in the array for a first time period and turning off said transfer switches at the end of said first time period;

(2) turning on the reset switches of all storage pixel sensors in the array for a reset period occurring during a first portion of said first time period and turning off said reset switches at the end of said first portion of said first time period;

(3) integrating photocurrent in all storage pixel sensors in the array for an integration period occurring during a second portion of said first time period after said reset switches have been turned off, said integration period ending at the end of said first time period;

(4) turning on the reset switches of all storage pixel sensors in the array for a reference period after the end of said first time period;

(5) selecting a row of the array and reading an output signal from each storage pixel sensor in the selected row; and

(6) repeating step (5) until output signals for all storage pixel sensors in all rows of the array have been read.

10. A method for operating an array of storage pixel sensors of claim 1 arranged in rows, including the steps of:

(1) turning on the transfer switches of all storage pixel sensors in the array for a first time period and turning off said transfer switches at the end of said first time period;

(2) turning on the reset switches of all storage pixel sensors in the array for a reset period occurring during a first portion of said first time period and turning off said reset switches at the end of said first portion of said first time period;

(3) integrating photocurrent in all storage pixel sensors in the array for an integration period occurring during a second portion of said first time period after said reset switches have been turned off, said integration period ending at the end of said first time period;

(4) turning on the reset switches of all storage pixel sensors in the array for a reference period after the end of said first time period;

(5) selecting a row of the array, reading an output signal from each storage pixel sensor in the selected row, then activating the transfer switches of all storage pixel sensors in the selected row and reading a reference signal from each storage pixel sensor in the selected row, then taking the difference between the output signal and the reference signal for each storage pixel sensor in the selected row; and

(6) repeating step (5) until output signals and reference signals for all storage pixel sensors in all rows of the array have been read and correlated double sampled.

11. An array of storage pixel sensors disposed on a semiconductor substrate, the array comprising:

a plurality of storage pixel sensors, each storage pixel sensor including;

a capacitive storage element having a first terminal connected to a fixed potential and a second terminal;

a photodiode having a first terminal connected to a first potential and a second terminal;

a semiconductor reset switch having a first terminal connected to said second terminal of said photodiode and a second terminal connected to a reset potential that reverse biases said photodiode;

a semiconductor transfer switch having a first terminal connected to said second terminal of said photodiode and a second terminal connected to said second terminal of said capacitive storage element;

a semiconductor amplifier having an input connected to said second terminal of said capacitive storage element and an output;

said semiconductor reset switch and said semiconductor transfer switch each having a control element for selectively activating said semiconductor reset switch and said semiconductor transfer switch;

a light shield disposed over portions of the semiconductor substrate comprising a circuit node including said second terminal of said semiconductor transfer switch, said second terminal of said capacitive storage element and said input of said semiconductor amplifier and to prevent substantially all photons from entering said circuit node; and

minority carrier rejection means for preventing substantially all minority carriers generated in said semiconductor substrate from entering said circuit node;

means for generating a reset signal and for coupling said reset signal to the control elements of all reset switches in the array;

means for generating a global transfer signal and for coupling said global transfer signal to the control elements of all transfer switches in the array;

means for generating a row transfer signal for each row in the array and for coupling the row transfer signal for each row to the control elements of all transfer switches associated with that row; and

a column line for each column in the array, each column line coupled to the outputs of the ones of the semiconductor amplifier associated with that column.

12. The array of claim 11 wherein each storage pixel sensor further includes a semiconductor select switch having an input connected to the output of said amplifier, an output connected to an output bus, and a control element connected to said control circuit.

13. The array of claim 11 wherein:

said semiconductor substrate is formed from a semiconductor material of a first conductivity type;

said light shield in each storage pixel sensor is a portion of a metal interconnect layer disposed over said semiconductor substrate;

said semiconductor transfer switch in each storage pixel sensor comprises a MOS transistor of a second conductivity type opposite said first conductivity type, said MOS transistor formed in a well of said first conductivity type, said well disposed in said semiconductor substrate, wherein said minority carrier rejection means comprises said well.

14. The array of claim 11 wherein:

said semiconductor substrate is formed from a semiconductor material of a first conductivity type;

said light shield in each storage pixel sensor is a portion of a metal interconnect layer disposed over said semiconductor substrate;

said semiconductor transfer switch in each storage pixel sensor comprises a MOS transistor of said first conductivity type formed in a well of a second conductivity type opposite said first conductivity type, said well disposed in said semiconductor substrate, wherein said minority carrier rejection means comprises said well.

15. The array of claim 11 wherein:

said semiconductor substrate is p-type semiconductor substrate;

said light shield in each storage pixel sensor is a portion of a metal interconnect layer disposed over said semiconductor substrate;

said semiconductor transfer switch in each storage pixel sensor comprises an N-Channel MOS transistor formed in a p-well formed in said p-type semiconductor substrate, wherein said minority carrier rejection means comprises said p-well.

16. The array of claim 11 wherein:

said semiconductor substrate is p-type semiconductor substrate;

said light shield in each storage pixel sensor is a portion of a metal interconnect layer disposed over said semiconductor substrate;

said semiconductor transfer switch in each storage pixel sensor comprises a P-Channel MOS transistor formed in an n-well formed in said p-type semiconductor substrate, wherein said minority carrier rejection means comprises said n-well.

17. An array of storage pixel sensors disposed on a semiconductor substrate, the array comprising:

a plurality of storage pixel sensors, each storage pixel sensor including;

a capacitive storage element having a first terminal connected to a fixed potential and a second terminal;

a photodiode having a first terminal connected to a first potential and a second terminal;

a semiconductor reset switch having a first terminal connected to said second terminal of said photodiode and a second terminal connected to a reset potential that reverse biases said photodiode;

a semiconductor transfer switch having a first terminal connected to said second terminal of said photodiode and a second terminal connected to said second terminal of said capacitive storage element;

a semiconductor amplifier having an input connected to said second terminal of said capacitive storage element and an output;

said semiconductor reset switch and said semiconductor transfer switch each having a control element for selectively activating said semiconductor reset switch and said semiconductor transfer switch;

a light shield disposed over portions of the semiconductor substrate comprising a circuit node including said second terminal of said semiconductor transfer switch, said second terminal of said capacitive storage element and said input of said semiconductor amplifier and to prevent substantially all photons from entering said circuit node; and

minority carrier rejection means for preventing substantially all minority carriers generated in said semiconductor substrate from entering said circuit node;

means for generating a reset signal and for coupling said reset signal to the control elements of all reset switches in the array;

means for generating a transfer signal and for coupling said transfer signal to the control elements of all transfer switches in the array; and

a column line for each column in the array, each column line coupled to the outputs of the ones of the semiconductor amplifier associated with that column.

18. The array of claim 17 wherein each storage pixel sensor further includes a semiconductor select switch having an input connected to the output of said amplifier, an output connected to an output bus, and a control element connected to said control circuit.

19. The array of claim 17 wherein:

said semiconductor substrate is formed from a semiconductor material of a first conductivity type;

said light shield in each storage pixel sensor is a portion of a metal interconnect layer disposed over said semiconductor substrate;

said semiconductor transfer switch in each storage pixel sensor comprises a MOS transistor of a second conductivity type opposite said first conductivity type, said MOS transistor formed in a well of said first conductivity type, said well disposed in said semiconductor substrate, wherein said minority carrier rejection means comprises said well.

20. The array of claim 17 wherein:

said semiconductor substrate is formed from a semiconductor material of a first conductivity type;

said light shield in each storage pixel sensor is a portion of a metal interconnect layer disposed over said semiconductor substrate;

said semiconductor transfer switch in each storage pixel sensor comprises a MOS transistor of said first conductivity type formed in a well of a second conductivity type opposite said first conductivity type, said well disposed in said semiconductor substrate, wherein said minority carrier rejection means comprises said well.

21. The array of claim 17 wherein:

said semiconductor substrate is p-type semiconductor substrate;

said light shield in each storage pixel sensor is a portion of a metal interconnect layer disposed over said semiconductor substrate;

said semiconductor transfer switch in each storage pixel sensor comprises an N-Channel MOS transistor formed in a p-well formed in said p-type semiconductor substrate, wherein said minority carrier rejection means comprises said p-well.

22. The array of claim 17 wherein:

said semiconductor substrate is p-type semiconductor substrate;

said light shield in each storage pixel sensor is a portion of a metal interconnect layer disposed over said semiconductor substrate;

said semiconductor transfer switch in each storage pixel sensor comprises a P-Channel MOS transistor formed in an n-well formed in said p-type semiconductor substrate, wherein said minority carrier rejection means comprises said n-well.