Raid XOR operations to synchronous DRAM using a read buffer and pipelining of synchronous DRAM burst read data

• US 6,370,611 B1
• Filed: 04/04/2000
• Issued: 04/09/2002
• Est. Priority Date: 04/04/2000
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Callison, Ryan A., Galloway, William C., Garza, Christopher, Chang, Albert H.
• Primary Examiner(s): Peikari, B
• Application Number:
  US09/542,624
• Time in Patent Office: 735 Days
• Field of Search: 711/105, 711/114, 711/169, 711/155, 710/35, 714/6, 708/232
• US Class Current: 711/105
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 2211/1054 Parity-fast hardware, i.e. dedicated fast hardware for RAID systems with parity
• CPC Class Codes: G06F 2211/1066 Parity-small-writes, i.e. improved small or partial write techniques in RAID systems

Abstract

A memory interface controller includes a read buffer to pipeline data from a synchronous dynamic random access memory (DRAM) in response to a plurality of consecutive SDRAM burst read requests, a write buffer to store write data, an exclusive or (XOR) engine to XOR the write data with the data from the read buffer, and a write interface to write resulting data from XORing the write data and the data from the read buffer to the synchronous DRAM. Data is pipelined in the read buffer by repeatedly issuing an SDRAM burst read request before data is transferred out of the synchronous DRAM in response to a previous SDRAM burst read request until a desired amount of data is stored in the read buffer. The memory interface controller thus can perform an external read-modify-write cycle for the synchronous DRAM. The synchronous DRAM can serve as a RAID (Redundant Array s of Inexpensive Disks) memory.

Claims

1. A memory interface controller, comprising:

a read buffer to pipeline read data from a synchronous dynamic random access memory (SDRAM) in response to a plurality of consecutive SDRAM burst read requests;

a write buffer to store write data;

an exclusive or (XOR) engine to XOR the write data with read data from the read buffer; and

a write interface to write the resulting data from XORing the write data and the date from the read buffer to the synchronous dynamic random access memory.

2. The memory interface controller of claim 1, wherein the synchronous dynamic random access memory serves as a RAID (Redundant Arrays Inexpensive Disks) memory.

3. The memory interface controller of claim 1, wherein the write data comprises peripheral component interconnect (PCI) data.

4. The memory interface controller of claim 1, wherein an SDRAM burst read request is issued before the read data is transferred out of the synchronous dynamic random access memory in response to a previous SDRAM burst read request.

5. A method of performing an external read-modify-write cycle for a synchronous DRAM (dynamic random access memory), comprising the steps of:

pipelining data from a synchronous dynamic random access memory (SDRAM) in a read buffer in response to a plurality of consecutive SDRAM burst read requests;

storing write data in a write buffer;

XORing the write data with the data from the read buffer; and

writing the resulting data from XORing the write data with the data from the read buffer to the synchronous dynamic random access memory.

6. The method of claim 5, wherein the synchronous dynamic random access memory serves as a RAID (Redundant Arrays Inexpensive Disks) memory.

7. The method of claim 5, wherein the write data comprises peripheral component interconnect (PCI) data.

8. The method of claim 5, further comprising the step of:

issuing an SDRAM burst read request before data is transferred out of the synchronous DRAM in response to a previous SDRAM burst read request.

9. A bus/memory interface device, comprising:

a synchronous dynamic random access memory controller to control a synchronous dynamic random access memory; and

a memory interface controller coupled to the synchronous dynamic random access memory controller, the memory interface controller comprising;

a read buffer to pipeline data from the synchronous dynamic random access memory (SDRAM) in response to a plurality of consecutive SDRAM burst read requests;

a write buffer to store write data;

an exclusive or (XOR) engine to XOR the write data with data from the read buffer; and

a write interface to write the resulting data from XORing the write data and the data from the read buffer to the synchronous dynamic random access memory.

10. The bus/memory interface device of claim 9, wherein the synchronous dynamic random access memory controller serves as a RAID (Redundant Arrays Inexpensive Disks) memory controller.

11. The bus/memory interface device of claim 9, wherein the write data comprises peripheral component interconnect (PCI) data.

12. A memory interface controller, comprising:

a means for pipelining data from a synchronous dynamic random access memory (SDRAM) in response to a plurality of consecutive SDRAM burst read requests;

a means to store write data;

a means to XOR the write data with the data from the synchronous dynamic random access memory; and

a means to write resulting data from XORing the write data and the data from the synchronous dynamic random access memory to the synchronous dynamic random access memory.

13. The memory interface controller of claim 12, wherein the synchronous dynamic random access memory serves as a RAID (Redundant Arrays Inexpensive Disks) memory.

14. The memory controller of claim 12, wherein the write data comprises peripheral component interconnect (PCI) data.

15. The memory controller of claim 12, further comprising:

a means for issuing an SDRAM burst read request before data is transferred out of the synchronous dynamic random access memory in response to a previous SDRAM burst read request.