Method and apparatus that enforces a regional memory model in hierarchical memory systems

• US 6,370,632 B1
• Filed: 11/18/1998
• Issued: 04/09/2002
• Est. Priority Date: 11/18/1997
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Intrinsity Incorporated (Apple Inc.)
• Inventors: Kikuta, Betty Y., Potter, Terence M., Blomgren, James S.
• Primary Examiner(s): Kim, Matthew M.
• Assistant Examiner(s): CHACE, CHRISTIAN
• Application Number:
  US09/195,758
• Time in Patent Office: 1,238 Days
• Field of Search: 711/147, 711/205, 711/206
• US Class Current: 711/205
• CPC Class Codes: G06F 12/0837 with software control, e.g. non-cacheable data
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/681 Multi-level TLB, e.g. microTLB and main TLB

Abstract

The present invention discloses a method and apparatus that uses extensions to the TLB entry to dynamically identify pages of memory that can be weakly ordered or must be strongly ordered and enforces the appropriate memory model on those pages of memory. Such identification and memory model enforcement allows for more efficient execution of memory instructions in a hierarchical memory design in cases where memory instructions can be executed out of order. From the page table, the memory manager constructs TLB entries that associate page frame numbers of memory operands with page-granular client usage data and a memory order tag. The memory order tag identifies the memory model that is currently being enforced for the associated page of memory. The memory manager updates the memory order tag of the TLB entry in accordance with changes in the client usage information. In the preferred embodiment, the TLB structure is a global TLB shared by all processors. In alternative embodiments, the TLB structure may comprise either multiple distributed TLBs with shared knowledge, each assigned to a different processor, or a combination of multiple local TLBs, each assigned to a different processor, that exchange information with a global TLB, which in turn provides data to the memory manager to access the hierarchical memory system.

Claims

1. A memory manager that dynamically enforces a memory model in non-cache memory, comprising:

a plurality of memory-owning clients executing a computer program, said memory-owning clients issue memory instructions;

a page table that identifies an initial memory model to be enforced on each page of non-cache memory and an initial list of which of said memory-owning clients are authorized to access each page of non-cache memory;

a translation lookaside buffer (TLB) comprising a plurality of TLB entries, each said TLB entry includes a physical address, virtual address, and the memory model and client usage associated with said physical and virtual addresses, wherein said memory model and said client usage are initialized from said page table; and

a memory manager that intercepts said memory instructions, updates said memory model and said client usage in said TLB entry, and queues said memory instruction for execution according to said memory model, wherein said update is performed according to at least one of the following criteria;

memory type, client usage, and elapsed time between accesses.

5. A dependent claim according to claim 1, 2, 3, or 4 wherein said computer program further comprises a computer program that does not include memory synchronization commands.

6. A dependent claim according to claim 1, 2, 3, or 4 wherein said memory manager updates said memory model in said TLB entry to a strong memory model when said client usage indicates that two or more of said memory-owning clients are authorized to access said physical and virtual addresses and said physical address corresponds to non-cache memory that is not read-only memory.

7. A dependent claim according to claim 1, 2, 3, or 4 wherein said memory manager updates said memory model in said TLB entry to a strong memory model when said client usage indicates that said memory-owning client authorized to access said physical and virtual addresses comprises a processor capable of executing speculative and out-of-order memory instructions.

8. A dependent claim according to claim 1, 2, 3, or 4 wherein said memory manager updates said memory model in said TLB entry from a strong memory model to a weak memory model when said client usage indicates that only one of said memory-owning clients is authorized to access said physical and virtual addresses.

9. A dependent claim according to claim 1, 2, 3, or 4 wherein said memory manager updates said memory model in said TLB entry from a strong memory model to a weak memory model when said client usage indicates that two or more of said memory-owning clients are authorized to access said physical and virtual addresses but said accesses are separated by a preselected elapsed time.

2. A memory management system that dynamically enforces a memory model in non-cache memory, comprising:

a plurality of memory-owning clients executing a computer program, said memory-owning clients issue memory instructions;

a page table that identifies an initial memory model to be enforced on each page of non-cache memory and an initial list of which of said memory-owning clients are authorized to access each page of non-cache memory;

a translation lookaside buffer (TLB) comprising a plurality of TLB entries, each said TLB entry includes a physical address, virtual address, and the memory model and client usage associated with said physical and virtual addresses, wherein said memory model and said client usage are initialized from said page table; and

a memory manager that intercepts said memory instructions, updates said memory model and said client usage in said TLB entry, and queues said memory instruction for execution according to said memory model, wherein said update is performed according to at least one of the following criteria;

memory type, client usage, and elapsed time between accesses.

3. A method that makes a memory manager that dynamically enforces a memory model in non-cache memory, comprising:

providing a plurality of memory-owning clients executing a computer program, said memory-owning clients issue memory instructions;

providing a page table that identifies an initial memory model to be enforced on each page of non-cache memory and an initial list of which of said memory-owning clients are authorized to access each page of non-cache memory;

providing a translation lookaside buffer (TLB) comprising a plurality of TLB entries, each said TLB entry includes a physical address, virtual address, and the memory model and client usage associated with said physical and virtual addresses, wherein said memory model and said client usage are initialized from said page table; and

providing a memory manager that intercepts said memory instructions, updates said memory model and said client usage in said TLB entry, and queues said memory instruction for execution according to said memory model, wherein said update is performed according to at least one of the following criteria;

memory type, client usage, and elapsed time between accesses.

4. A method that dynamically enforces a memory model in non-cache memory, comprising:

executing a computer program using a plurality of memory-owning clients that issue memory instructions;

identifying an initial memory model to be enforced on each page of non-cache memory and an initial list of which of said plurality of memory-owning clients are authorized to access each page of non-cache memory in a page table;

generating a plurality of TLB entries in a translation lookaside buffer, each said TLB entry includes a physical address, virtual address, and the memory model and client usage associated with said physical and virtual addresses, wherein said memory model and said client usage are initialized from said page table; and

intercepting said memory instructions using a memory manager, updating said memory model and said client usage in said TLB entry, and queuing said memory instruction for execution according to said memory model, wherein said update is performed according to at least one of the following criteria;

memory type, client usage, and elapsed time between accesses.